diff options
| author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-30 12:12:19 +0000 |
|---|---|---|
| committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-30 12:12:19 +0000 |
| commit | 7384652668585517500084ebf0c10e2946758f05 (patch) | |
| tree | 657ad81ab9d251f7540f9b8bf75c5ee57b720622 /test/CodeGen/Hexagon | |
| parent | 996d6ddb49d9353fce795894a7be554f69f3e3ed (diff) | |
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
As part of the unification of the debug format and the MIR format, avoid
printing "vreg" for virtual registers (which is one of the current MIR
possibilities).
Basically:
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g"
* grep -nr '%vreg' . and fix if needed
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g"
* grep -nr 'vreg[0-9]\+' . and fix if needed
Differential Revision: https://reviews.llvm.org/D40420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319427 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Hexagon')
| -rw-r--r-- | test/CodeGen/Hexagon/circ_ldd_bug.ll | 8 | ||||
| -rw-r--r-- | test/CodeGen/Hexagon/expand-condsets-rm-reg.mir | 4 | ||||
| -rw-r--r-- | test/CodeGen/Hexagon/post-inc-aa-metadata.ll | 2 |
3 files changed, 7 insertions, 7 deletions
diff --git a/test/CodeGen/Hexagon/circ_ldd_bug.ll b/test/CodeGen/Hexagon/circ_ldd_bug.ll index d15b5c964eb..40584cae7b0 100644 --- a/test/CodeGen/Hexagon/circ_ldd_bug.ll +++ b/test/CodeGen/Hexagon/circ_ldd_bug.ll @@ -7,10 +7,10 @@ target triple = "hexagon" ; UNREACHABLE executed at llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp:615! ; This happened because after unrolling a loop with a ldd_circ instruction we ; would have several TFCR and ldd_circ instruction sequences. -; %vreg0 (CRRegs) = TFCR %vreg0 (IntRegs) -; = ldd_circ( , , vreg0) -; %vreg1 (CRRegs) = TFCR %vreg1 (IntRegs) -; = ldd_circ( , , vreg0) +; %0 (CRRegs) = TFCR %0 (IntRegs) +; = ldd_circ( , , %0) +; %1 (CRRegs) = TFCR %1 (IntRegs) +; = ldd_circ( , , %0) ; The scheduler would move the CRRegs to the top of the loop. The allocator ; would try to spill the CRRegs after running out of them. We don't have code to ; spill CRRegs and the above assertion would be triggered. diff --git a/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir b/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir index e4c54c4b988..550e5c55550 100644 --- a/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir +++ b/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir @@ -3,12 +3,12 @@ # Check that coalesced registers are removed from live intervals. # -# Check that vreg3 is coalesced into vreg4, and that after coalescing +# Check that %3 is coalesced into %4, and that after coalescing # it is no longer in live intervals. # CHECK-LABEL: After expand-condsets # CHECK: INTERVALS -# CHECK-NOT: vreg3 +# CHECK-NOT: %3 # CHECK: MACHINEINSTRS diff --git a/test/CodeGen/Hexagon/post-inc-aa-metadata.ll b/test/CodeGen/Hexagon/post-inc-aa-metadata.ll index 673a9b41ff2..688a71352cd 100644 --- a/test/CodeGen/Hexagon/post-inc-aa-metadata.ll +++ b/test/CodeGen/Hexagon/post-inc-aa-metadata.ll @@ -3,7 +3,7 @@ ; Check that the generated post-increment load has TBAA information. ; CHECK-LABEL: Machine code for function fred: -; CHECK: = V6_vL32b_pi %vreg{{[0-9]+}}<tied1>, 64; mem:LD64[{{.*}}](tbaa= +; CHECK: = V6_vL32b_pi %{{[0-9]+}}<tied1>, 64; mem:LD64[{{.*}}](tbaa= target triple = "hexagon" |