[Hexagon] Allow construction of HVX vector predicates

Handle BUILD_VECTOR of boolean values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321220 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 45 insertions, 9 deletions

diff --git a/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll b/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll
new file mode 100644
index 00000000000..f96dbf2af49
--- /dev/null
+++ b/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll
@@ -0,0 +1,19 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Check that this doesn't crash.
+; CHECK: sfcmp
+
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+target triple = "hexagon"
+
+define void @fred() #0 {
+b0:
+  %v1 = load <16 x float>, <16 x float>* null, align 8
+  %v2 = fcmp olt <16 x float> undef, %v1
+  %v3 = select <16 x i1> %v2, <16 x i16> undef, <16 x i16> zeroinitializer
+  %v4 = sext <16 x i16> %v3 to <16 x i32>
+  store <16 x i32> %v4, <16 x i32>* undef, align 64
+  unreachable
+}
+
+attributes #0 = { noinline norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
diff --git a/test/CodeGen/Hexagon/autohvx/isel-bool-vector.ll b/test/CodeGen/Hexagon/autohvx/isel-bool-vector.ll
new file mode 100644
index 00000000000..4cbd00837fc
--- /dev/null
+++ b/test/CodeGen/Hexagon/autohvx/isel-bool-vector.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Check that this testcase doesn't crash.
+; CHECK: sfcmp
+
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+target triple = "hexagon"
+
+define void @fred() #0 {
+b0:
+  %v1 = fcmp olt <16 x float> zeroinitializer, undef
+  %v2 = select <16 x i1> %v1, <16 x i16> undef, <16 x i16> zeroinitializer
+  %v3 = sext <16 x i16> %v2 to <16 x i32>
+  store <16 x i32> %v3, <16 x i32>* undef, align 128
+  unreachable
+}
+
+attributes #0 = { noinline norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b" }
diff --git a/test/CodeGen/Hexagon/expand-vstorerw-undef.ll b/test/CodeGen/Hexagon/expand-vstorerw-undef.ll
index 88eaec938fd..5ac0f59bd2d 100644
--- a/test/CodeGen/Hexagon/expand-vstorerw-undef.ll
+++ b/test/CodeGen/Hexagon/expand-vstorerw-undef.ll
@@ -12,7 +12,7 @@
 
 ; CHECK-LABEL: fred:
 ; CHECK: v[[REG:[0-9]+]] = vsplat
-; CHECK: vmem(r29+#6) = v[[REG]]
+; CHECK: vmem(r29+#{{[0-9]+}}) = v[[REG]]
 
 
 target triple = "hexagon"
diff --git a/test/CodeGen/Hexagon/v60-cur.ll b/test/CodeGen/Hexagon/v60-cur.ll
index 26d40c9a697..d0ffe1d8fdd 100644
--- a/test/CodeGen/Hexagon/v60-cur.ll
+++ b/test/CodeGen/Hexagon/v60-cur.ll
@@ -1,9 +1,8 @@
-; RUN: llc -march=hexagon -enable-pipeliner=false < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 
 ; Test that we generate a .cur
 
-; CHECK: v{{[0-9]*}}.cur{{ *}}
-; CHECK: v{{[0-9]*}}.cur{{ *}}
+; CHECK: v{{[0-9]*}}.cur
 
 define void @conv3x3_i(i8* noalias nocapture readonly %iptr0, i32 %shift, i32 %width) #0 {
 entry:
diff --git a/test/CodeGen/Hexagon/vect/vect-infloop.ll b/test/CodeGen/Hexagon/vect/vect-infloop.ll
index 4de390159fd..9ee0b0ab3aa 100644
--- a/test/CodeGen/Hexagon/vect/vect-infloop.ll
+++ b/test/CodeGen/Hexagon/vect/vect-infloop.ll
@@ -1,10 +1,10 @@
 ; Extracted from test/CodeGen/Generic/vector-casts.ll: used to loop indefinitely.
 ; RUN: llc -march=hexagon < %s | FileCheck %s
-; CHECK: combine
+; CHECK: convert_df2w
 
 define void @a(<2 x double>* %p, <2 x i8>* %q) {
-        %t = load <2 x double>, <2 x double>* %p
-	%r = fptosi <2 x double> %t to <2 x i8>
-        store <2 x i8> %r, <2 x i8>* %q
-	ret void
+  %t = load <2 x double>, <2 x double>* %p
+  %r = fptosi <2 x double> %t to <2 x i8>
+  store <2 x i8> %r, <2 x i8>* %q
+  ret void
 }