[Hexagon] Adjust patterns to reflect instruction selection preferences

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316804 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 59 insertions, 2 deletions

diff --git a/test/CodeGen/Hexagon/isel-prefer.ll b/test/CodeGen/Hexagon/isel-prefer.ll
new file mode 100644
index 00000000000..062b0b3a0ea
--- /dev/null
+++ b/test/CodeGen/Hexagon/isel-prefer.ll
@@ -0,0 +1,57 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+@data1 = external global [2 x [31 x i8]], align 8
+@data2 = external global [2 x [91 x i8]], align 8
+
+; CHECK-LABEL: Prefer_M4_or_andn:
+; CHECK: r2 |= and(r0,~r1)
+define i32 @Prefer_M4_or_andn(i32 %a0, i32 %a1, i32 %a2) #0 {
+b3:
+  %v4 = xor i32 %a1, -1
+  %v5 = shl i32 %a2, 5
+  %v6 = and i32 %a0, %v4
+  %v7 = or i32 %v6, %v5
+  ret i32 %v7
+}
+
+; CHECK-LABEL: Prefer_M4_mpyri_addi:
+; CHECK: add(##data1,mpyi(r0,#31))
+define i32 @Prefer_M4_mpyri_addi(i32 %a0) #0 {
+b1:
+  %v2 = getelementptr inbounds [2 x [31 x i8]], [2 x [31 x i8]]* @data1, i32 0, i32 %a0
+  %v3 = ptrtoint [31 x i8]* %v2 to i32
+  ret i32 %v3
+}
+
+; CHECK-LABEL: Prefer_M4_mpyrr_addi:
+; CHECK: add(##data2,mpyi(r0,r1))
+define i32 @Prefer_M4_mpyrr_addi(i32 %a0) #0 {
+b1:
+  %v2 = getelementptr inbounds [2 x [91 x i8]], [2 x [91 x i8]]* @data2, i32 0, i32 %a0
+  %v3 = ptrtoint [91 x i8]* %v2 to i32
+  ret i32 %v3
+}
+
+; CHECK-LABEL: Prefer_S2_tstbit_r:
+; CHECK: p0 = tstbit(r0,r1)
+define i32 @Prefer_S2_tstbit_r(i32 %a0, i32 %a1) #0 {
+b2:
+  %v3 = shl i32 1, %a1
+  %v4 = and i32 %a0, %v3
+  %v5 = icmp ne i32 %v4, 0
+  %v6 = zext i1 %v5 to i32
+  ret i32 %v6
+}
+
+; CHECK-LABEL: Prefer_S2_ntstbit_r:
+; CHECK: p0 = !tstbit(r0,r1)
+define i32 @Prefer_S2_ntstbit_r(i32 %a0, i32 %a1) #0 {
+b2:
+  %v3 = shl i32 1, %a1
+  %v4 = and i32 %a0, %v3
+  %v5 = icmp eq i32 %v4, 0
+  %v6 = zext i1 %v5 to i32
+  ret i32 %v6
+}
+
+attributes #0 = { nounwind readnone }
diff --git a/test/CodeGen/Hexagon/swp-stages4.ll b/test/CodeGen/Hexagon/swp-stages4.ll
index f58e8320315..8e8d977c684 100644
--- a/test/CodeGen/Hexagon/swp-stages4.ll
+++ b/test/CodeGen/Hexagon/swp-stages4.ll
@@ -11,9 +11,9 @@
 ; CHECK: loop0(.LBB0_[[LOOP:.]],
 ; CHECK: .LBB0_[[LOOP]]:
 ; CHECK: [[REG0]] += add
+; CHECK: [[REG2:r[0-9]+]] = and
 ; CHECK: = and
-; CHECK: = and
-; CHECK: [[REG0]] = and
+; CHECK: [[REG0]] = [[REG2]]
 ; CHECK: endloop
 
 ; Function Attrs: nounwind