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| author | Coby Tayree <coby.tayree@intel.com> | 2017-11-21 09:11:41 +0000 |
|---|---|---|
| committer | Coby Tayree <coby.tayree@intel.com> | 2017-11-21 09:11:41 +0000 |
| commit | f6e1efe78a87e6f174582549b337c47c2c69db92 (patch) | |
| tree | 2918c31e3945069ed6343ec02b6c4449b088e2d9 /lib/Target/X86/X86.td | |
| parent | f9cc39148ab38031f8ba7957360f61ef0d483b9c (diff) | |
[x86][icelake]VAES introduction
an icelake promotion of AES
Differential Revision: https://reviews.llvm.org/D40078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318740 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86.td')
| -rw-r--r-- | lib/Target/X86/X86.td | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td index 62aab840258..5c7bb0045c8 100644 --- a/lib/Target/X86/X86.td +++ b/lib/Target/X86/X86.td @@ -172,6 +172,9 @@ def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem", def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", "Enable AES instructions", [FeatureSSE2]>; +def FeatureVAES : SubtargetFeature<"vaes", "HasVAES", "true", + "Promote selected AES instructions to AVX512/AVX registers", + [FeatureAVX, FeatureAES]>; def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true", "Enable TBM instructions">; def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true", |