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authorCraig Topper <craig.topper@intel.com>2017-10-15 16:57:33 +0000
committerCraig Topper <craig.topper@intel.com>2017-10-15 16:57:33 +0000
commitab9ea0ecca45e6f8dff7c198f9a09037a1988f6f (patch)
tree3ae465c4bd6cac6e5c0c079f9fa41991f0747625 /lib/Target/X86/X86.td
parent8ceb11ff2e1728d46b216f9eae1e6399fc522b95 (diff)
[X86] Remove the SlowBTMem feature flag entirely
Turns out we have no patterns on the instructions that were using this feature flag for other reasons. These instructions are slow on all modern CPUs so it seems unlikely that we will spend any effort supporting these instructions going forward. So we might as well just kill of the feature flag and just fix up the comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315862 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86.td')
-rw-r--r--lib/Target/X86/X86.td73
1 files changed, 25 insertions, 48 deletions
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td
index 2e7902a6064..03b5a6064c9 100644
--- a/lib/Target/X86/X86.td
+++ b/lib/Target/X86/X86.td
@@ -95,8 +95,6 @@ def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
"64-bit with cmpxchg16b",
[Feature64Bit]>;
-def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
- "Bit testing of memory is slow">;
def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
"SHLD instruction is slow">;
def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
@@ -336,7 +334,7 @@ def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
def : Proc<"pentium3", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
FeatureSSE1, FeatureFXSR]>;
def : Proc<"pentium3m", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
- FeatureSSE1, FeatureFXSR, FeatureSlowBTMem]>;
+ FeatureSSE1, FeatureFXSR]>;
// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
// The intent is to enable it for pentium4 which is the current default
@@ -350,7 +348,7 @@ def : Proc<"pentium3m", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
def : ProcessorModel<"pentium-m", GenericPostRAModel,
[FeatureX87, FeatureSlowUAMem16, FeatureMMX,
- FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
+ FeatureSSE2, FeatureFXSR]>;
def : ProcessorModel<"pentium4", GenericPostRAModel,
[FeatureX87, FeatureSlowUAMem16, FeatureMMX,
@@ -358,7 +356,7 @@ def : ProcessorModel<"pentium4", GenericPostRAModel,
def : ProcessorModel<"pentium4m", GenericPostRAModel,
[FeatureX87, FeatureSlowUAMem16, FeatureMMX,
- FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
+ FeatureSSE2, FeatureFXSR]>;
// Intel Quark.
def : Proc<"lakemont", []>;
@@ -366,20 +364,19 @@ def : Proc<"lakemont", []>;
// Intel Core Duo.
def : ProcessorModel<"yonah", SandyBridgeModel,
[FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
- FeatureFXSR, FeatureSlowBTMem]>;
+ FeatureFXSR]>;
// NetBurst.
def : ProcessorModel<"prescott", GenericPostRAModel,
[FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
- FeatureFXSR, FeatureSlowBTMem]>;
+ FeatureFXSR]>;
def : ProcessorModel<"nocona", GenericPostRAModel, [
FeatureX87,
FeatureSlowUAMem16,
FeatureMMX,
FeatureSSE3,
FeatureFXSR,
- FeatureCMPXCHG16B,
- FeatureSlowBTMem
+ FeatureCMPXCHG16B
]>;
// Intel Core 2 Solo/Duo.
@@ -390,7 +387,6 @@ def : ProcessorModel<"core2", SandyBridgeModel, [
FeatureSSSE3,
FeatureFXSR,
FeatureCMPXCHG16B,
- FeatureSlowBTMem,
FeatureLAHFSAHF,
FeatureMacroFusion
]>;
@@ -401,7 +397,6 @@ def : ProcessorModel<"penryn", SandyBridgeModel, [
FeatureSSE41,
FeatureFXSR,
FeatureCMPXCHG16B,
- FeatureSlowBTMem,
FeatureLAHFSAHF,
FeatureMacroFusion
]>;
@@ -416,7 +411,6 @@ class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
FeatureFXSR,
FeatureCMPXCHG16B,
FeatureMOVBE,
- FeatureSlowBTMem,
FeatureLEAForSP,
FeatureSlowDivide32,
FeatureSlowDivide64,
@@ -444,7 +438,6 @@ class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
FeaturePRFCHW,
FeatureSlowLEA,
FeatureSlowIncDec,
- FeatureSlowBTMem,
FeatureSlowPMULLD,
FeatureLAHFSAHF
]>;
@@ -466,7 +459,6 @@ class GoldmontProc<string Name> : ProcessorModel<Name, SLMModel, [
FeatureSlowTwoMemOps,
FeatureSlowLEA,
FeatureSlowIncDec,
- FeatureSlowBTMem,
FeatureLAHFSAHF,
FeatureMPX,
FeatureSHA,
@@ -488,7 +480,6 @@ class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
FeatureSSE42,
FeatureFXSR,
FeatureCMPXCHG16B,
- FeatureSlowBTMem,
FeaturePOPCNT,
FeatureLAHFSAHF,
FeatureMacroFusion
@@ -504,7 +495,6 @@ class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
FeatureSSE42,
FeatureFXSR,
FeatureCMPXCHG16B,
- FeatureSlowBTMem,
FeaturePOPCNT,
FeatureAES,
FeaturePCLMUL,
@@ -547,7 +537,6 @@ def SNBFeatures : ProcessorFeatures<[], [
class SandyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
SNBFeatures.Value, [
- FeatureSlowBTMem,
FeatureSlowUAMem32
]>;
def : SandyBridgeProc<"sandybridge">;
@@ -561,7 +550,6 @@ def IVBFeatures : ProcessorFeatures<SNBFeatures.Value, [
class IvyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
IVBFeatures.Value, [
- FeatureSlowBTMem,
FeatureSlowUAMem32
]>;
def : IvyBridgeProc<"ivybridge">;
@@ -579,8 +567,7 @@ def HSWFeatures : ProcessorFeatures<IVBFeatures.Value, [
class HaswellProc<string Name> : ProcModel<Name, HaswellModel,
HSWFeatures.Value, [
- ProcIntelHSW,
- FeatureSlowBTMem
+ ProcIntelHSW
]>;
def : HaswellProc<"haswell">;
def : HaswellProc<"core-avx2">; // Legacy alias.
@@ -591,8 +578,7 @@ def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [
]>;
class BroadwellProc<string Name> : ProcModel<Name, HaswellModel,
BDWFeatures.Value, [
- ProcIntelBDW,
- FeatureSlowBTMem
+ ProcIntelBDW
]>;
def : BroadwellProc<"broadwell">;
@@ -608,8 +594,7 @@ def SKLFeatures : ProcessorFeatures<BDWFeatures.Value, [
class SkylakeClientProc<string Name> : ProcModel<Name, SkylakeClientModel,
SKLFeatures.Value, [
- ProcIntelSKL,
- FeatureSlowBTMem
+ ProcIntelSKL
]>;
def : SkylakeClientProc<"skylake">;
@@ -632,7 +617,6 @@ def KNLFeatures : ProcessorFeatures<IVBFeatures.Value, [
class KnightsLandingProc<string Name> : ProcModel<Name, HaswellModel,
KNLFeatures.Value, [
ProcIntelKNL,
- FeatureSlowBTMem,
FeatureSlowTwoMemOps,
FeatureFastPartialYMMorZMMWrite
]>;
@@ -641,7 +625,6 @@ def : KnightsLandingProc<"knl">;
class KnightsMillProc<string Name> : ProcModel<Name, HaswellModel,
KNLFeatures.Value, [
ProcIntelKNL,
- FeatureSlowBTMem,
FeatureSlowTwoMemOps,
FeatureFastPartialYMMorZMMWrite
]>;
@@ -659,8 +642,7 @@ def SKXFeatures : ProcessorFeatures<SKLFeatures.Value, [
class SkylakeServerProc<string Name> : ProcModel<Name, SkylakeServerModel,
SKXFeatures.Value, [
- ProcIntelSKX,
- FeatureSlowBTMem
+ ProcIntelSKX
]>;
def : SkylakeServerProc<"skylake-avx512">;
def : SkylakeServerProc<"skx">; // Legacy alias.
@@ -673,8 +655,7 @@ def CNLFeatures : ProcessorFeatures<SKXFeatures.Value, [
class CannonlakeProc<string Name> : ProcModel<Name, HaswellModel,
CNLFeatures.Value, [
- ProcIntelCNL,
- FeatureSlowBTMem
+ ProcIntelCNL
]>;
def : CannonlakeProc<"cannonlake">;
@@ -684,46 +665,43 @@ def : Proc<"k6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
def : Proc<"athlon", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
- FeatureSlowBTMem, FeatureSlowSHLD]>;
+ FeatureSlowSHLD]>;
def : Proc<"athlon-tbird", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
- FeatureSlowBTMem, FeatureSlowSHLD]>;
-def : Proc<"athlon-4", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
- Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
FeatureSlowSHLD]>;
+def : Proc<"athlon-4", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
+ Feature3DNowA, FeatureFXSR, FeatureSlowSHLD]>;
def : Proc<"athlon-xp", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
- Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
- FeatureSlowSHLD]>;
+ Feature3DNowA, FeatureFXSR, FeatureSlowSHLD]>;
def : Proc<"athlon-mp", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
- Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
- FeatureSlowSHLD]>;
+ Feature3DNowA, FeatureFXSR, FeatureSlowSHLD]>;
def : Proc<"k8", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
Feature3DNowA, FeatureFXSR, Feature64Bit,
- FeatureSlowBTMem, FeatureSlowSHLD]>;
+ FeatureSlowSHLD]>;
def : Proc<"opteron", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
Feature3DNowA, FeatureFXSR, Feature64Bit,
- FeatureSlowBTMem, FeatureSlowSHLD]>;
+ FeatureSlowSHLD]>;
def : Proc<"athlon64", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
Feature3DNowA, FeatureFXSR, Feature64Bit,
- FeatureSlowBTMem, FeatureSlowSHLD]>;
+ FeatureSlowSHLD]>;
def : Proc<"athlon-fx", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
Feature3DNowA, FeatureFXSR, Feature64Bit,
- FeatureSlowBTMem, FeatureSlowSHLD]>;
+ FeatureSlowSHLD]>;
def : Proc<"k8-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
- FeatureSlowBTMem, FeatureSlowSHLD]>;
+ FeatureSlowSHLD]>;
def : Proc<"opteron-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
- FeatureSlowBTMem, FeatureSlowSHLD]>;
+ FeatureSlowSHLD]>;
def : Proc<"athlon64-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
- FeatureSlowBTMem, FeatureSlowSHLD]>;
+ FeatureSlowSHLD]>;
def : Proc<"amdfam10", [FeatureX87, FeatureSSE4A, Feature3DNowA,
FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
- FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
+ FeaturePOPCNT, FeatureSlowSHLD,
FeatureLAHFSAHF]>;
def : Proc<"barcelona", [FeatureX87, FeatureSSE4A, Feature3DNowA,
FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
- FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
+ FeaturePOPCNT, FeatureSlowSHLD,
FeatureLAHFSAHF]>;
// Bobcat
@@ -929,7 +907,6 @@ def : ProcessorModel<"x86-64", SandyBridgeModel, [
FeatureFXSR,
Feature64Bit,
FeatureSlow3OpsLEA,
- FeatureSlowBTMem,
FeatureSlowIncDec,
FeatureMacroFusion
]>;