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authorPeter Collingbourne <peter@pcc.me.uk>2018-05-21 17:57:19 +0000
committerPeter Collingbourne <peter@pcc.me.uk>2018-05-21 17:57:19 +0000
commita8e9721d8de743d0610782cd65b22875945ee393 (patch)
tree71b3538c95c14efa10e17bbbb715a358034ba898 /lib/Target/RISCV
parentc2406964f339a7e40cef3d9419d9645a9ad838a8 (diff)
MC: Change MCAsmBackend::writeNopData() to take a raw_ostream instead of an MCObjectWriter. NFCI.
To make this work I needed to add an endianness field to MCAsmBackend so that writeNopData() implementations know which endianness to use. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47035 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332857 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/RISCV')
-rw-r--r--lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp11
1 files changed, 6 insertions, 5 deletions
diff --git a/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index 5b5663b07d0..87088092164 100644
--- a/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -33,7 +33,8 @@ class RISCVAsmBackend : public MCAsmBackend {
public:
RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit)
- : MCAsmBackend(), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit) {}
+ : MCAsmBackend(support::little), STI(STI), OSABI(OSABI),
+ Is64Bit(Is64Bit) {}
~RISCVAsmBackend() override {}
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
@@ -100,7 +101,7 @@ public:
MCInst &Res) const override;
- bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
};
@@ -188,7 +189,7 @@ bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
}
-bool RISCVAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
+bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC];
unsigned MinNopLen = HasStdExtC ? 2 : 4;
@@ -198,13 +199,13 @@ bool RISCVAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
// The canonical nop on RISC-V is addi x0, x0, 0.
uint64_t Nop32Count = Count / 4;
for (uint64_t i = Nop32Count; i != 0; --i)
- OW->write32(0x13);
+ OS.write("\x13\0\0\0", 4);
// The canonical nop on RVC is c.nop.
if (HasStdExtC) {
uint64_t Nop16Count = (Count - Nop32Count * 4) / 2;
for (uint64_t i = Nop16Count; i != 0; --i)
- OW->write16(0x01);
+ OS.write("\x01\0", 2);
}
return true;