diff options
| author | Mandeep Singh Grang <mgrang@codeaurora.org> | 2018-04-16 18:56:10 +0000 |
|---|---|---|
| committer | Mandeep Singh Grang <mgrang@codeaurora.org> | 2018-04-16 18:56:10 +0000 |
| commit | 9d2fcc2bf4a301d05d9b440a805847645637ab28 (patch) | |
| tree | b91b5ea4bf8c704c47af349609b413a29ab30f75 /lib/Target/RISCV | |
| parent | 9a56b66b35c9d18f40a4b7012d73331c2a0cf55b (diff) | |
[RISCV] Fix assert message operator
Summary:
Specifying assert message with an || operator makes the compiler interpret it
as a bool. Changed it to &&.
Reviewers: asb, apazos
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, llvm-commits
Differential Revision: https://reviews.llvm.org/D45660
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330148 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/RISCV')
| -rw-r--r-- | lib/Target/RISCV/RISCVISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/RISCV/RISCVISelLowering.cpp b/lib/Target/RISCV/RISCVISelLowering.cpp index 0018a9c750f..1d2a15c319b 100644 --- a/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/lib/Target/RISCV/RISCVISelLowering.cpp @@ -658,7 +658,7 @@ static bool CC_RISCV(const DataLayout &DL, unsigned ValNo, MVT ValVT, MVT LocVT, // Handle passing f64 on RV32D with a soft float ABI. if (XLen == 32 && ValVT == MVT::f64) { - assert(!ArgFlags.isSplit() && PendingLocs.empty() || + assert(!ArgFlags.isSplit() && PendingLocs.empty() && "Can't lower f64 if it is split"); // Depending on available argument GPRS, f64 may be passed in a pair of // GPRs, split between a GPR and the stack, or passed completely on the |