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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-10-13 21:10:22 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-10-13 21:10:22 +0000 |
| commit | 93f0e0c1d118ec2f7fb84050c9810e9e6846d438 (patch) | |
| tree | 8e93109e84e9d376421a4db59b8162961687c95c /lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | 39ba348795c0552ee59468805f19363b588f74ca (diff) | |
AMDGPU: Implement hasBitPreservingFPLogic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315754 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | lib/Target/AMDGPU/SIISelLowering.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp index 2bc3d7fa508..82d1bc270a4 100644 --- a/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3107,6 +3107,10 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter( } } +bool SITargetLowering::hasBitPreservingFPLogic(EVT VT) const { + return isTypeLegal(VT.getScalarType()); +} + bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const { // This currently forces unfolding various combinations of fsub into fma with // free fneg'd operands. As long as we have fast FMA (controlled by |