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| author | Chad Rosier <mcrosier@codeaurora.org> | 2017-09-25 14:05:00 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2017-09-25 14:05:00 +0000 |
| commit | 6aaf3f7809366cb759061440fde43fbdc88fec14 (patch) | |
| tree | 03e0ee915fedadeedf0d725aca8313d0a3098398 /lib/Target/AArch64/AArch64.td | |
| parent | ad0d5b1b249fc4b241dff80bf3322159f630f918 (diff) | |
[AArch64] Add basic support for Qualcomm's Saphira CPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314105 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64.td')
| -rw-r--r-- | lib/Target/AArch64/AArch64.td | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64.td b/lib/Target/AArch64/AArch64.td index 8d2934ee8ab..500632b50cd 100644 --- a/lib/Target/AArch64/AArch64.td +++ b/lib/Target/AArch64/AArch64.td @@ -348,6 +348,20 @@ def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor", FeatureSlowSTRQro ]>; +def ProcSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", + "Qualcomm Saphira processors", [ + FeatureCrypto, + FeatureCustomCheapAsMoveHandling, + FeatureFPARMv8, + FeatureNEON, + FeatureSPE, + FeaturePerfMon, + FeaturePostRAScheduler, + FeaturePredictableSelectIsExpensive, + FeatureZCZeroing, + FeatureLSLFast, + HasV8_3aOps]>; + def ProcThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily", "ThunderX2T99", "Cavium ThunderX2 processors", [ @@ -426,6 +440,7 @@ def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>; def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>; def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM2]>; def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>; +def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>; def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>; // Cavium ThunderX/ThunderX T8X Processors def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>; |