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| author | Florian Hahn <florian.hahn@arm.com> | 2017-06-15 09:31:23 +0000 |
|---|---|---|
| committer | Florian Hahn <florian.hahn@arm.com> | 2017-06-15 09:31:23 +0000 |
| commit | 4127960e358b6a412e9b39a4d0c4dce16555946a (patch) | |
| tree | 088d5592c99e5101f89a459aded90f550da9d915 /lib/Target/AArch64/AArch64.td | |
| parent | 952d4e50f594d14548a2b4ad38296110ff09da14 (diff) | |
[AArch64] Enable FeatureFuseAES for the generic processor model.
Summary:
Scheduling AESE/AESMC and AESD/AESIMC instruction pairs back-to-back
gives a double digit speedup on benchmarks using those instructions on
Cortex-A processors. In GCC, this optimization is part of the generic
processor model as well.
This change should not have a major performance impact on processors
that do not optimize AES instruction pairs, although I only had access
to Cortex-A processors for benchmarking.
Reviewers: rengolin, kristof.beyls, javed.absar, evandro, silviu.baranga, MatzeB, mcrosier, joelkevinjones, joel_k_jones, bmakam, t.p.northover
Reviewed By: evandro
Subscribers: sbaranga, aemerson, llvm-commits
Differential Revision: https://reviews.llvm.org/D33836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305457 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64.td')
| -rw-r--r-- | lib/Target/AArch64/AArch64.td | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64.td b/lib/Target/AArch64/AArch64.td index abe28460c83..53eef79c4df 100644 --- a/lib/Target/AArch64/AArch64.td +++ b/lib/Target/AArch64/AArch64.td @@ -362,6 +362,7 @@ def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily", def : ProcessorModel<"generic", NoSchedModel, [ FeatureFPARMv8, + FeatureFuseAES, FeatureNEON, FeaturePerfMon, FeaturePostRAScheduler |