diff options
| author | Krzysztof Kozlowski <k.kozlowski@samsung.com> | 2016-05-11 14:02:08 +0200 |
|---|---|---|
| committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2016-06-02 11:18:08 +0200 |
| commit | 880c81b3b6604a004d56b5975c8bed47276e8bf6 (patch) | |
| tree | 9ddae9c2cdadf9c3481b61f0be551c7c6d850295 /drivers/clk/samsung | |
| parent | ad98c64fbb792d7089118b6568ce7bc35fce1875 (diff) | |
clk: samsung: exynos5440: Constify all clock initializers
All of initialization data can be made const.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5440.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c index 22c73d4a5ee3..a57d01b99b76 100644 --- a/drivers/clk/samsung/clk-exynos5440.c +++ b/drivers/clk/samsung/clk-exynos5440.c @@ -35,7 +35,7 @@ static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initda }; /* fixed rate clocks */ -static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = { +static const struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initconst = { FRATE(0, "ppll", NULL, 0, 1000000000), FRATE(0, "usb_phy0", NULL, 0, 60000000), FRATE(0, "usb_phy1", NULL, 0, 60000000), @@ -44,26 +44,26 @@ static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = }; /* fixed factor clocks */ -static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initconst = { FFACTOR(0, "div250", "ppll", 1, 4, 0), FFACTOR(0, "div200", "ppll", 1, 5, 0), FFACTOR(0, "div125", "div250", 1, 2, 0), }; /* mux clocks */ -static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = { +static const struct samsung_mux_clock exynos5440_mux_clks[] __initconst = { MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1), MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p, CPU_CLK_STATUS, 0, 1, "armclk"), }; /* divider clocks */ -static struct samsung_div_clock exynos5440_div_clks[] __initdata = { +static const struct samsung_div_clock exynos5440_div_clks[] __initconst = { DIV(CLK_SPI_BAUD, "div_spi", "mout_spi", MISC_DOUT1, 3, 2), }; /* gate clocks */ -static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = { +static const struct samsung_gate_clock exynos5440_gate_clks[] __initconst = { GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0), GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0), GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0), |