diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2018-01-19 16:55:29 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-05-25 16:46:17 +0200 |
| commit | 3ede9f3e4b247b3cff5f260c10a860e87cf19109 (patch) | |
| tree | b9f49d36e8dc5382c3eb687e38cc2315cb1d6015 | |
| parent | e3f208839a172f1c18335ac28de6684f1fb85066 (diff) | |
clk: meson: axg: add the fractional part of the fixed_pll
[ Upstream commit 6b71aceceb09918daf37a40a1221077599040be3 ]
The fixed_pll also has a fractional part. On axg s400 board, without
this parameter, the calculated rate is off by ~8Mhz (0,4%). The fixed_pll
being the root of the peripheral clock tree, this error is propagated to
the rest of the clocks
Adding the definition of the parameter fixes the problem
Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/clk/meson/axg.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index c568add0fcef..3b8b53b279dc 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -129,6 +129,11 @@ static struct meson_clk_pll axg_fixed_pll = { .shift = 16, .width = 2, }, + .frac = { + .reg_off = HHI_MPLL_CNTL2, + .shift = 0, + .width = 12, + }, .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "fixed_pll", |