gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c


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/* { dg-do compile } */
/* { dg-options "-march=armv8-a+nolse -O2" } */

#include "atomic-op-seq_cst.x"

/* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */