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path: root/gcc/config/aarch64/aarch64.c
AgeCommit message (Expand)Author
2019-08-30aarch64: X-Gene: Adapt tuning struct for GCC 8.Christoph Muellner
2019-08-30[AArch64] Fix in xgene1_addrcost_table.Christoph Muellner
2019-08-30[AArch64] Add Xgene1 prefetch tunings.Christoph Muellner
2019-08-30aarch64: eMAG/Xgene: Procedural cost-model for X-Gene processors.Christoph Muellner
2019-08-30[aarch64] Add CPU support for Ampere Computing's eMAG.Christoph Muellner
2019-08-30aarch64: Correct the maximum shift amount for shifted operands.Philipp Tomsich
2019-08-30aarch64: Retpoline (Spectre-V2 mitigation) for aarch64.Christoph Muellner
2019-01-08 Backported from mainlinejakub
2018-10-16[AArch64] Fix PR87511wilco
2018-09-25i2018-09-24 Andrew Pinski <apinski@marvell.com>pinskia
2018-08-29[AArch64, Falkor] Switch to using Falkor-specific vector costs.luisgpm
2018-08-29[aarch64] Adjust Falkor's sign extend reg+reg address costluisgpm
2018-07-04[AArch64, Falkor] Falkor address costs tuningluisgpm
2018-03-152018-03-15 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>rguenth
2018-03-05[AArch64] PR84114: Avoid reassociating FMAwilco
2018-02-28 * config/aarch64/aarch64.c (aarch64_emit_probe_stack_range): Removeebotcazou
2018-02-222018-02-22 Steve Ellcey <sellcey@cavium.com>sje
2018-02-21Add "native" as a valid option value for -march= on aarch64 (PR driver/83193).marxin
2018-02-20Fix missing info for -march and -mtune wrong values on aarch64 (PR driver/831...marxin
2018-02-08[AArch64] Use more LDP/STP in shrinkwrappingwilco
2018-02-01[PR83370][AARCH64]Use tighter register constraint for sibcall patterns.renlin
2018-02-01[AArch64] Handle SVE subregs that are effectively REVsrsandifo
2018-02-01[AArch64] Prefer LD1RQ for big-endian SVErsandifo
2018-02-01[AArch64] Use all SVE LD1RQ variantsrsandifo
2018-02-01[AArch64] Generalise aarch64_simd_valid_immediate for SVErsandifo
2018-02-01[AArch64] Tighten aarch64_secondary_reload condition (PR 83845)rsandifo
2018-01-18[AArch64] Fix fp16 test failures after PR82964 fixwilco
2018-01-17[AArch64] PR82964: Fix 128-bit immediate ICEswilco
2018-01-13Rework the legitimize_address_displacement hookrsandifo
2018-01-13Add an "early rematerialisation" passrsandifo
2018-01-13Add an empty_mask_is_expensive hookrsandifo
2018-01-13[AArch64] SVE load/store_lanes supportrsandifo
2018-01-13[AArch64] Add SVE supportrsandifo
2018-01-11[AArch64] Add const_offset field to aarch64_address_inforsandifo
2018-01-11[AArch64] Set NUM_POLY_INT_COEFFS to 2rsandifo
2018-01-11[AArch64] Rework interface to add constant/offset routinesrsandifo
2018-01-11[AArch64] Extra scalar_float_mode patchrsandifo
2018-01-09[AArch64] Use vec_perm_indices helper routinesrsandifo
2018-01-09[AArch64] Reject (high (const (plus anchor offset)))rsandifo
2018-01-08gcc/vp
2018-01-03[AArch64] Rewrite aarch64_simd_valid_immediatersandifo
2018-01-03 Update copyright years.jakub
2018-01-03poly_int: vec_perm_indices element typersandifo
2018-01-03poly_int: current_vector_size and TARGET_AUTOVECTORIZE_VECTOR_SIZESrsandifo
2018-01-02Make vec_perm_indices use new vector encodingrsandifo
2018-01-02Remove vec_perm_const optabrsandifo
2017-12-21[patch AArch64] Do not perform a vector splat for vector initialisation if it...jgreenhalgh
2017-12-21[AArch64] Tweak aarch64_classify_address interfacersandifo
2017-12-16poly_int: IN_TARGET_CODErsandifo
2017-12-14[PATCH PR81228][AARCH64]Fix ICE by adding LTGT in vec_cmp<mode><v_int_equiv>sudi
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