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2020-05-11c++: Avoid unnecessary deprecated warnings.Jason Merrill
There's no need to warn that a deprecated function uses a deprecated type, that just adds noise. We were preventing that in start_decl, but that didn't help member declarations that go through grokfield. So handle it in grokdeclarator instead, which is shared between them. gcc/cp/ChangeLog 2020-05-11 Jason Merrill <jason@redhat.com> * decl.c (grokdeclarator): Adjust deprecated_state here. (start_decl): Not here.
2020-05-11i386: Add V2SFmode sqrt insn pattern [PR95046]Uros Bizjak
gcc/ChangeLog: 2020-05-11 Uroš Bizjak <ubizjak@gmail.com> PR target/95046 * config/i386/mmx.md (sqrtv2sf2): New insn pattern. testsuite/ChangeLog: 2020-05-11 Uroš Bizjak <ubizjak@gmail.com> PR target/95046 * gcc.target/i386/pr95046-1.c (test_sqrt): Add.
2020-05-11rs6000: Add vcfuged instructionKelvin Nilsen
Add the new vector centrifuge-doubleword instruction and built-in function access. [gcc] 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org> * config/rs6000/altivec.h (vec_cfuge): New #define. * config/rs6000/altivec.md (UNSPEC_VCFUGED): New constant. (vcfuged): New insn. * config/rs6000/rs6000-builtin.def (__builtin_altivec_vcfuged): New built-in function. * config/rs6000/rs6000-call.c (builtin_function_type): Add handling for FUTURE_BUILTIN_VCFUGED case. * doc/extend.texi (PowerPC AltiVec Built-in Functions Available for a Future Architecture): Add description of vec_cfuge built-in function. [gcc/testsuite] 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org> * gcc.target/powerpc/vec-cfuged-0.c: New test. * gcc.target/powerpc/vec-cfuged-1.c: New test.
2020-05-11rs6000: Add scalar cfuged instructionKelvin Nilsen
Add the centifuge-doubleword instruction and built-in access. [gcc] 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org> * config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_0): New #define. (BU_FUTURE_MISC_1): Likewise. (BU_FUTURE_MISC_2): Likewise. (BU_FUTURE_MISC_3): Likewise. (__builtin_cfuged): New built-in function definition. * config/rs6000/rs6000.md (UNSPEC_CFUGED): New constant. (cfuged): New insn. * doc/extend.texi (Basic PowerPC Built-in Functions Available for a Future Architecture): New subsubsection. [gcc/testsuite] 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org> * gcc.target.powerpc/cfuged-0.c: New test. * gcc.target.powerpc/cfuged-1.c: New test.
2020-05-11tree-optimization/95049 - fix not terminating RPO VN iterationRichard Biener
This rejects lattice changes from one constant to another. 2020-05-11 Richard Biener <rguenther@suse.de> PR tree-optimization/95049 * tree-ssa-sccvn.c (set_ssa_val_to): Reject lattice transition between different constants. * gcc.dg/torture/pr95049.c: New testcase.
2020-05-11tree-pretty-print: Handle boolean typesRichard Sandiford
AVX512-style masks and SVE-style predicates can be difficult to debug in gimple dumps, since the types are printed like this: vector(4) <unnamed type> foo; Some important details are hidden by that <unnamed type>, such as the number of bits in an element and whether the type is signed or unsigned. This patch uses an ad-hoc syntax for printing unnamed boolean types. Normal frontend ones should be handled by the earlier TYPE_NAME code. 2020-05-11 Richard Sandiford <richard.sandiford@arm.com> gcc/ * tree-pretty-print.c (dump_generic_node): Handle BOOLEAN_TYPEs.
2020-05-11rs6000: Add vgnbKelvin Nilsen
Add support for the vgnb instruction, which gathers every Nth bit per vector element. [gcc] 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org> Bill Schmidt <wschmidt@linux.ibm.com> * config/rs6000/altivec.h (vec_gnb): New #define. * config/rs6000/altivec.md (UNSPEC_VGNB): New constant. (vgnb): New insn. * config/rs6000/rs6000-builtin.def (BU_FUTURE_OVERLOAD_1): New #define. (BU_FUTURE_OVERLOAD_2): Likewise. (BU_FUTURE_OVERLOAD_3): Likewise. (__builtin_altivec_gnb): New built-in function. (__buiiltin_vec_gnb): New overloaded built-in function. * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Define overloaded forms of __builtin_vec_gnb. (rs6000_expand_binop_builtin): Add error checking for 2nd argument of __builtin_vec_gnb. (builtin_function_type): Mark return value and arguments unsigned for FUTURE_BUILTIN_VGNB. * doc/extend.texi (PowerPC AltiVec Built-in Functions Available for a Future Architecture): Add description of vec_gnb built-in function. [gcc/testsuite] 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org> Bill Schmidt <wschmidt@linux.ibm.com> * gcc.target/powerpc/vec-gnb-0.c: New test. * gcc.target/powerpc/vec-gnb-1.c: New test. * gcc.target/powerpc/vec-gnb-10.c: New test. * gcc.target/powerpc/vec-gnb-2.c: New test. * gcc.target/powerpc/vec-gnb-3.c: New test. * gcc.target/powerpc/vec-gnb-4.c: New test. * gcc.target/powerpc/vec-gnb-5.c: New test. * gcc.target/powerpc/vec-gnb-6.c: New test. * gcc.target/powerpc/vec-gnb-7.c: New test. * gcc.target/powerpc/vec-gnb-8.c: New test. * gcc.target/powerpc/vec-gnb-9.c: New test.
2020-05-11rs6000: Add vector pdep/pextKelvin Nilsen
Add support for the vpdepd and vpextd instructions that perform vector parallel bit deposit and vector parallel bit extract. [gcc] 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org> Bill Schmidt <wschmidt@linux.ibm.com> * config/rs6000/altivec.h (vec_pdep): New macro implementing new built-in function. (vec_pext): Likewise. * config/rs6000/altivec.md (UNSPEC_VPDEPD): New constant. (UNSPEC_VPEXTD): Likewise. (vpdepd): New insn. (vpextd): Likewise. * config/rs6000/rs6000-builtin.def (__builtin_altivec_vpdepd): New built-in function. (__builtin_altivec_vpextd): Likewise. * config/rs6000/rs6000-call.c (builtin_function_type): Add handling for FUTURE_BUILTIN_VPDEPD and FUTURE_BUILTIN_VPEXTD cases. * doc/extend.texi (PowerPC Altivec Built-in Functions Available for a Future Architecture): Add description of vec_pdep and vec_pext built-in functions. [gcc/testsuite] 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org> * gcc.target/powerpc/vec-pdep-0.c: New. * gcc.target/powerpc/vec-pdep-1.c: New. * gcc.target/powerpc/vec-pext-0.c: New. * gcc.target/powerpc/vec-pext-1.c: New.
2020-05-11rs6000: Add vector count under maskKelvin Nilsen
Add support for new vclzdm and vctzdm vector instructions that count leading and trailing zeros under control of a mask. [gcc] 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org> Bill Schmidt <wschmidt@linux.ibm.com> * config/rs6000/altivec.h (vec_clzm): New macro. (vec_ctzm): Likewise. * config/rs6000/altivec.md (UNSPEC_VCLZDM): New constant. (UNSPEC_VCTZDM): Likewise. (vclzdm): New insn. (vctzdm): Likewise. * config/rs6000/rs6000-builtin.def (BU_FUTURE_V_0): New macro. (BU_FUTURE_V_1): Likewise. (BU_FUTURE_V_2): Likewise. (BU_FUTURE_V_3): Likewise. (__builtin_altivec_vclzdm): New builtin definition. (__builtin_altivec_vctzdm): Likewise. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Cause _ARCH_PWR_FUTURE macro to be defined if OPTION_MASK_FUTURE flag is set. * config/rs6000/rs6000-call.c (builtin_function_type): Set return value and parameter types to be unsigned for VCLZDM and VCTZDM. * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add support for TARGET_FUTURE flag. * config/rs6000/rs6000.h (RS6000_BTM_FUTURE): New macro constant. * doc/extend.texi (PowerPC Altivec Built-in Functions Available for a Future Architecture): New subsubsection. [gcc/testsuite] 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org> * gcc.target/powerpc/vec-clzm-0.c: New test. * gcc.target/powerpc/vec-clzm-1.c: New test. * gcc.target/powerpc/vec-ctzm-0.c: New test. * gcc.target/powerpc/vec-ctzm-1.c: New test.
2020-05-11tree-optimization/94988 - enhance SM some moreRichard Biener
This enhances store-order preserving store motion to handle the case of non-invariant dependent stores in the sequence of unconditionally executed stores on exit by re-issueing them as part of the sequence of stores on the exit. This fixes the observed regression of gcc.target/i386/pr64110.c which relies on store-motion of 'b' for a loop like for (int i = 0; i < j; ++i) *b++ = x; where for correctness we now no longer apply store-motion. With the patch we emit the correct tem = b; for (int i = 0; i < j; ++i) { tem = tem + 1; *tem = x; } b = tem; *tem = x; preserving the original order of stores. A testcase reflecting the miscompilation done by earlier GCC is added as well. This also fixes the reported ICE in PR95025 and adds checking code to catch it earlier - the issue was not-supported refs propagation leaving stray refs in the sequence. 2020-05-11 Richard Biener <rguenther@suse.de> PR tree-optimization/94988 PR tree-optimization/95025 * tree-ssa-loop-im.c (seq_entry): Make a struct, add from. (sm_seq_push_down): Take extra parameter denoting where we moved the ref to. (execute_sm_exit): Re-issue sm_other stores in the correct order. (sm_seq_valid_bb): When always executed, allow sm_other to prevail inbetween sm_ord and record their stored value. (hoist_memory_references): Adjust refs_not_supported propagation and prune sm_other from the end of the ordered sequences. * gcc.dg/torture/pr94988.c: New testcase. * gcc.dg/torture/pr95025.c: Likewise. * gcc.dg/torture/pr95045.c: Likewise. * g++.dg/asan/pr95025.C: New testcase.
2020-05-11[Fortran] Fix/modify present() handling for assumed-shape optional (PR 94672)Tobias Burnus
gcc/fortran/ 2020-05-07 Tobias Burnus <tobias@codesourcery.com> PR fortran/94672 * trans.h (gfc_conv_expr_present): Add use_saved_decl=false argument. * trans-expr.c (gfc_conv_expr_present): Likewise; use DECL directly and only if use_saved_decl is true, use the actual PARAM_DECL arg (saved descriptor). * trans-array.c (gfc_trans_dummy_array_bias): Set local 'arg.0' variable to NULL if 'arg' is not present. * trans-openmp.c (gfc_omp_check_optional_argument): Simplify by checking 'arg.0' instead of the true PARM_DECL. (gfc_omp_finish_clause): Remove setting 'arg.0' to NULL. gcc/testsuite/ 2020-05-07 Jakub Jelinek <jakub@redhat.com> Tobias Burnus <tobias@codesourcery.com> PR fortran/94672 * gfortran.dg/gomp/pr94672.f90: New. * gfortran.dg/missing_optional_dummy_6a.f90: Update scan-tree.
2020-05-11i386: Improve basic vectorized V2SFmode operations [PR95046]Uros Bizjak
Use plain "v" constraint for AVX alternatives and add "prefix" attribute. gcc/ChangeLog: PR target/95046 * config/i386/mmx.md (mmx_addv2sf3): Use "v" constraint instead of "Yv" for AVX alternatives. Add "prefix" attribute. (*mmx_addv2sf3): Ditto. (*mmx_subv2sf3): Ditto. (*mmx_mulv2sf3): Ditto. (*mmx_<code>v2sf3): Ditto. (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
2020-05-11aarch64: Fix ICE when expanding scalar floating move with ↵Fei Yang
-mgeneral-regs-only. [PR94991] In the testcase for PR94991, we are doing FAIL for scalar floating move expand pattern since TARGET_FLOAT is false with option -mgeneral-regs-only. But move expand pattern cannot fail. It would be better to replace the FAIL with code that bitcasts to the equivalent integer mode using gen_lowpart. 2020-05-11 Felix Yang <felix.yang@huawei.com> gcc/ PR target/94991 * config/aarch64/aarch64.md (mov<mode>): Bitcasts to the equivalent integer mode using gen_lowpart instead of doing FAIL for scalar floating point move. gcc/testsuite/ PR target/94991 * gcc.target/aarch64/mgeneral-regs_5.c: New test.
2020-05-11[PATCH] aarch64: prefer using csinv, csneg in zero extend contextsAlex Coplan
Given the C code: unsigned long long inv(unsigned a, unsigned b, unsigned c) { return a ? b : ~c; } Prior to this patch, AArch64 GCC at -O2 generates: inv: cmp w0, 0 mvn w2, w2 csel w0, w1, w2, ne ret and after applying the patch, we get: inv: cmp w0, 0 csinv w0, w1, w2, ne ret The new pattern also catches the optimization for the symmetric case where the body of foo reads a ? ~b : c. Similarly, with the following code: unsigned long long neg(unsigned a, unsigned b, unsigned c) { return a ? b : -c; } GCC at -O2 previously gave: neg: cmp w0, 0 neg w2, w2 csel w0, w1, w2, ne but now gives: neg: cmp w0, 0 csneg w0, w1, w2, ne ret with the corresponding code for the symmetric case as above. 2020-05-11 Alex Coplan <alex.coplan@arm.com> gcc/ * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Add case to correctly calculate cost for new pattern (*csinv3_uxtw_insn3). * config/aarch64/aarch64.md (*csinv3_utxw_insn1): New. (*csinv3_uxtw_insn2): New. (*csinv3_uxtw_insn3): New. * config/aarch64/iterators.md (neg_not_cs): New. gcc/testsuite/ * gcc.target/aarch64/csinv-neg.c: New test.
2020-05-11Fix missing files from previous commit.Kelvin Nilsen
2020-05-11rs6000: powerpc_future_ok and powerpc_future_hwKelvin Nilsen
Dejagnu targets for these. 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org> * gcc.target/powerpc/dg-future-0.c: New. * gcc.target/powerpc/dg-future-1.c: New. * lib/target-supports.exp (check_powerpc_future_hw_available): Replace -mfuture with -mcpu=future. (check_effective_target_powerpc_future_ok): Likewise. (is-effective-target): Add powerpc_future_hw.
2020-05-11testsuite: Require gnu-tm support for pr94856.CKito Cheng
- The testcase uses the -fgnu-tm option but does not ensure that support is enabled. This patch adds the test to the testcase. * gcc/testsuite/g++.dg/ipa/pr94856.C: Require fgnu-tm.
2020-05-11i386: Vectorize basic V2SFmode operations [PR94913]Uros Bizjak
Enable V2SFmode vectorization and vectorize V2SFmode PLUS, MINUS, MULT, MIN and MAX operations using XMM registers. To avoid unwanted secondary effects (e.g. exceptions), load values to XMM registers using MOVQ that clears high bits of the XMM register outside V2SFmode. The compiler now vectorizes e.g.: float r[2], a[2], b[2]; void test_plus (void) { for (int i = 0; i < 2; i++) r[i] = a[i] + b[i]; } to: movq a(%rip), %xmm0 movq b(%rip), %xmm1 addps %xmm1, %xmm0 movlps %xmm0, r(%rip) ret gcc/ChangeLog: PR target/95046 * config/i386/i386.c (ix86_vector_mode_supported_p): Vectorize 3dNOW! vector modes for TARGET_MMX_WITH_SSE. * config/i386/mmx.md (*mov<mode>_internal): Do not set mode of alternative 13 to V2SF for TARGET_MMX_WITH_SSE. (mmx_addv2sf3): Change operand predicates from nonimmediate_operand to register_mmxmem_operand. (addv2sf3): New expander. (*mmx_addv2sf3): Add SSE/AVX alternatives. Change operand predicates from nonimmediate_operand to register_mmxmem_operand. Enable instruction pattern for TARGET_MMX_WITH_SSE. (mmx_subv2sf3): Change operand predicate from nonimmediate_operand to register_mmxmem_operand. (mmx_subrv2sf3): Ditto. (subv2sf3): New expander. (*mmx_subv2sf3): Add SSE/AVX alternatives. Change operand predicates from nonimmediate_operand to register_mmxmem_operand. Enable instruction pattern for TARGET_MMX_WITH_SSE. (mmx_mulv2sf3): Change operand predicates from nonimmediate_operand to register_mmxmem_operand. (mulv2sf3): New expander. (*mmx_mulv2sf3): Add SSE/AVX alternatives. Change operand predicates from nonimmediate_operand to register_mmxmem_operand. Enable instruction pattern for TARGET_MMX_WITH_SSE. (mmx_<code>v2sf3): Change operand predicates from nonimmediate_operand to register_mmxmem_operand. (<code>v2sf3): New expander. (*mmx_<code>v2sf3): Add SSE/AVX alternatives. Change operand predicates from nonimmediate_operand to register_mmxmem_operand. Enable instruction pattern for TARGET_MMX_WITH_SSE. (mmx_ieee_<ieee_maxmin>v2sf3): Ditto. testsuite/ChangeLog: PR target/95046 * gcc.target/i386/pr95046-1.c: New test.
2020-05-11Fortran : Spurious warning message with -Wsurprising PR59107Mark Eggleston
This change is from a patch developed for gcc-5. The code has moved on since then requiring a change to interface.c 2020-05-11 Janus Weil <janus@gcc.gnu.org> Dominique d'Humieres <dominiq@lps.ens.fr> gcc/fortran/ PR fortran/59107 * gfortran.h: Rename field resolved as resolve_symbol_called and assign two 2 bits instead of 1. * interface.c (check_dtio_interface1): Use new field name. (gfc_find_typebound_dtio_proc): Use new field name. * resolve.c (gfc_resolve_intrinsic): Replace check of the formal field with resolve_symbol_called is at least 2, if it is not set the field to 2. (resolve_typebound_procedure): Use new field name. (resolve_symbol): Use new field name and check whether it is at least 1, if it is not set the field to 1. 2020-05-11 Mark Eggleston <markeggleston@gcc.gnu.org> gcc/testsuite/ PR fortran/59107 * gfortran.dg/pr59107.f90: New test.
2020-05-11Fix typo in fprofile-prefix-path.Martin Liska
PR c/95040 * common.opt: Fix typo in option description.
2020-05-11Add caveat about parsing of .gcda and .gcno files.Martin Liska
PR gcov-profile/94928 * gcov-io.h: Add caveat about coverage format parsing and possible outdated documentation.
2020-05-10Add handling of MULT_EXPR/PLUS_EXPR for wrapping overflow in affine ↵Xionghu Luo
combination(PR83403) Use determine_value_range to get value range info for fold convert expressions with internal operation PLUS_EXPR/MINUS_EXPR/MULT_EXPR when not overflow on wrapping overflow inner type. i.e.: (long unsigned int)((unsigned int)n * 10 + 1) => (long unsigned int)n * (long unsigned int)10 + (long unsigned int)1 With this patch for affine combination, load/store motion could detect more address refs independency and promote some memory expressions to registers within loop. PS: Replace the previous "(T1)(X + CST) as (T1)X - (T1)(-CST))" to "(T1)(X + CST) as (T1)X + (T1)(CST))" for wrapping overflow. Bootstrap and regression tested pass on Power8-LE. gcc/ChangeLog 2020-05-11 Xiong Hu Luo <luoxhu@linux.ibm.com> PR tree-optimization/83403 * tree-affine.c (expr_to_aff_combination): Replace SSA_NAME with determine_value_range, Add fold conversion of MULT_EXPR, fix the previous PLUS_EXPR. gcc/testsuite/ChangeLog 2020-05-11 Xiong Hu Luo <luoxhu@linux.ibm.com> PR tree-optimization/83403 * gcc.dg/tree-ssa/pr83403-1.c: New test. * gcc.dg/tree-ssa/pr83403-2.c: New test. * gcc.dg/tree-ssa/pr83403.h: New header.
2020-05-11Daily bump.GCC Administrator
2020-05-10i386: Define __ILP32__ and _ILP32 for all 32-bit targetsGerald Pfeifer
* config/i386/i386-c.c (ix86_target_macros): Define _ILP32 and __ILP32__ for 32-bit targets.
2020-05-10PR fortran/93499 - ICE on division by zero in declaration statementsHarald Anlauf
Division by zero in declaration statements could sometimes generate NULL pointers being passed around that lead to ICEs. 2020-05-10 Harald Anlauf <anlauf@gmx.de> gcc/fortran/ PR fortran/93499 * arith.c (gfc_divide): Catch division by zero. (eval_intrinsic_f3): Safeguard for NULL operands. gcc/testsuite/ PR fortran/93499 * gfortran.dg/pr93499.f90: New test.
2020-05-10Daily bump.GCC Administrator
2020-05-09Update copyright yearEric Botcazou
2020-05-09Add assertion for access attributesEric Botcazou
* gcc-interface/trans.c (Attribute_to_gnu) <Attr_Access>: Assert that the prefix is not a type.
2020-05-09Fix small issues with -fgnat-encodings=minimalEric Botcazou
This is the mode where the GNAT compiler does not use special encodings in the debug info to describe some Ada constructs, for example packed array types. * gcc-interface/ada-tree.h (TYPE_PACKED_ARRAY_TYPE_P): Rename into... (TYPE_BIT_PACKED_ARRAY_TYPE_P): ...this. (TYPE_IS_PACKED_ARRAY_TYPE_P): Rename into... (BIT_PACKED_ARRAY_TYPE_P): ...this. (TYPE_IMPL_PACKED_ARRAY_P): Adjust to above renaming. * gcc-interface/gigi.h (maybe_pad_type): Remove IS_USER_TYPE.. * gcc-interface/decl.c (gnat_to_gnu_entity) <E_Variable>: Adjust call to maybe_pad_type. <E_Ordinary_Fixed_Point_Type>: Remove const qualifiers for tree. <E_Signed_Integer_Subtype>: Remove redundant test and redundant call to associate_original_type_to_packed_array. Turn into assertion. Call associate_original_type_to_packed_array and modify gnu_entity_name accordingly. Explicitly set the parallel type for GNAT encodings. Call create_type_decl in the misaligned case before maybe_pad_type. <E_Array_Type>: Do not use the name of the implementation type for a packed array when not using GNAT encodings. <E_Array_Subtype>: Move around setting flags. Use the result of the call to associate_original_type_to_packed_array for gnu_entity_name. <E_Record_Subtype>: Create XVS type and XVZ variable only if debug info is requested for the type. Call create_type_decl if a padded type was created for a type entity (gnat_to_gnu_component_type): Use local variable and adjust calls to maybe_pad_type. (gnat_to_gnu_subprog_type): Adjust call to maybe_pad_type. (gnat_to_gnu_field): Likewise. (validate_size): Adjust to renaming of macro. (set_rm_size): Likewise. (associate_original_type_to_packed_array): Adjust return type and return the name of the original type if GNAT encodings are not used * gcc-interface/misc.c (gnat_get_debug_typ): Remove obsolete stuff. (gnat_get_fixed_point_type_info): Remove const qualifiers for tree. (gnat_get_array_descr_info): Likewise and set variables lazily. Remove call to maybe_debug_type. Simplify a few computations. (enumerate_modes): Remove const qualifier for tree. * gcc-interface/utils.c (make_type_from_size): Adjust to renaming. (maybe_pad_type): Remove IS_USER_TYPE parameter and adjust. Remove specific code for implementation types for packed arrays. (compute_deferred_decl_context): Remove const qualifier for tree. (convert): Adjust call to maybe_pad_type. (unchecked_convert): Likewise. * gcc-interface/utils2.c (is_simple_additive_expressio): Likewise.
2020-05-09Fix tree sharing issue with slicesEric Botcazou
This can happen because we build an array type on the fly in case there is an apparent type inconsistency in the construct. * gcc-interface/utils2.c (build_binary_op) <ARRAY_RANGE_REF>: Use build_nonshared_array_type to build the common type and declare it.
2020-05-09Do not override -fnon-call-exceptions in default modeEric Botcazou
This was already the case in -gnatp mode. * gcc-interface/misc.c (gnat_init_gcc_eh): Do not override the user for -fnon-call-exceptions in default mode.
2020-05-09Do not make a local copy of large aggregateEric Botcazou
This prevents gigi from making a local copy of large aggregates. * gcc-interface/trans.c (lvalue_required_p) <N_Selected_Component>: Merge with N_Slice. <N_Allocator>: Move to... (lvalue_for_aggregate_p): ...here. New function. (Identifier_to_gnu): For an identifier with aggregate type, also call lvalue_for_aggregate_p if lvalue_required_p returned false before substituting the identifier with the constant.
2020-05-09Fix problematic cases of wrappingEric Botcazou
* gcc-interface/trans.c (gnat_to_gnu): Do not wrap boolean values if they appear in any kind of attribute references.
2020-05-09Accept qualified aggregates in memset pathEric Botcazou
Aggregates can be surrounded by a qualified expression and this prepares the support code in gigi for accepting them. * gcc-interface/trans.c (gnat_to_gnu) <N_Assignment_Statement>: Deal with qualified "others" aggregates in the memset case.
2020-05-09Fix missing back-annotation for Out parameterEric Botcazou
This happens when it is passed by copy and not passed in. * gcc-interface/decl.c (gnat_to_gnu_param): Also back-annotate the mechanism in the case of an Out parameter only passed by copy-out.
2020-05-09Small housekeeping work in gigiEric Botcazou
No functional changes. * gcc-interface/gigi.h (change_qualified_type): Move around. (maybe_vector_array): Likewise. (maybe_padded_object): New static line function. * gcc-interface/trans.c (Attribute_to_gnu) <Attr_Component_Size>: Remove useless code. <Attr_Null_Parameter>: Remove obsolete code. (Call_to_gn): Likewise. Use maybe_padded_object to remove padding. (gnat_to_gnu): Likewise. <N_String_Literal>: Do not add a useless null character at the end. <N_Indexed_Component>: Likewise and remove obsolete code. (add_decl_expr): Likewise. (maybe_implicit_deref): Likewise. * gcc-interface/utils.c (maybe_unconstrained_array): Likewise. * gcc-interface/utils2.c (gnat_invariant_expr): Likewise.
2020-05-09Remove last use of expr_alignEric Botcazou
It was in the ada/gcc-interface repository and is outdated. * tree.h (expr_align): Delete. * tree.c (expr_align): Likewise. ada/ * gcc-interface/utils2.c: Include builtins.h. (known_alignment) <ADDR_EXPR>: Use DECL_ALIGN for DECL_P operands and get_object_alignment for the rest.
2020-05-09testsuite: Fix up two testcases [PR95008]Jakub Jelinek
two-types-6.c never emitted the warning, even in 4.5/4.6, and pr93382.c doesn't have properly escaped parens, so doesn't check whether they are literally present in the message. 2020-05-09 Jakub Jelinek <jakub@redhat.com> PR testsuite/95008 * gcc.dg/two-types-6.c: Remove dg-warning directive that never triggered. * gcc.dg/analyzer/pr93382.c: Properly escape ()s in the diagnostic message.
2020-05-09cris: Enable "neg" to set condition codes.Hans-Peter Nilsson
While gcc seems to prefer transforming tests on the result of reversible operations, into tests on the original, it also can work with the destination, if allocated to the same register as it commonly-enough is. The re-use is easily covered in a test-case. (N.B.: the value 0x80000000 appears to be considered invalid and unimportant.) Spotted as a "microregression" in libgcc when comparing to the cc0 version. gcc: * config/cris/cris.c (cris_select_cc_mode): Return CC_NZmode for NEG too. Correct comment. * config/cris/cris.md ("<anz>neg<mode>2<setnz>"): Rename from "neg<mode>2".
2020-05-09cris: Enable single-bit btst/btstq to set condition codes.Hans-Peter Nilsson
Enables the use of btst / btstq for a single bit (at other bits than 0, including as indicated by a variable) to set condition-codes. There's also a bug-fix for the bit-0-btstq pattern; it shouldn't generate CCmode as only the Z flag is valid, still using CC_NZmode is ok, as only equality-tests are generated. The cris_rtx_costs tweak is necessary or else combine will consider the btst not preferable. It reduces the difference to cc0-costs beyond the threshold to the transformation being seen as profitable, but there's still a difference in values for the pre-split-time btst+branch as opposed to the cc0 btst and branch, with both appearing to be the cost of several insns (18 and 22). gcc: * config/cris/cris-modes.def (CC_ZnN): New CC_MODE. * config/cris/cris.c (cris_rtx_costs): Handle pre-split bit-test * config/cris/cris.md (ZnNNZSET, ZnNNZUSE): New mode_iterators. (znnCC, rznnCC): New code_attrs. ("*btst<mode>"): Iterator over ZnNNZSET instead of NZVCSET. Remove obseolete comment. Add belt-and-suspenders mode-test to condition. Add fixme regarding remaining matched-but-not-generated case. ("*cbranch<mode>4_btstrq1_<CC>"): New insn_and_split. ("*cbranch<mode>4_btstqb0_<CC>"): Rename from "*cbranch<mode>4_btstq<CC>". Split to CC_NZ instead of CC. ("*b<zcond:code><mode>"): Iterate over ZnNNZUSE instead of NZUSE. Handle output of CC_ZnNmode. ("*b<nzcond:code>_reversed<mode>"): Ditto.
2020-05-09cris: Enable 32-bit shifts, clz, bswap, umin to set condition codes.Hans-Peter Nilsson
Enables dropping of compares with zero of the result, through any CCmode substitution. gcc: * config/cris/cris.md ("<acc><anz><anzvc><shlr>si3<setcc><setnz><setnzvc>"): Rename from "<shlr>si3". ("<acc><anz><anzvc>clzsi2<setcc><setnz><setnzvc>"): Rename from "clzsi2". ("<acc><anz><anzvc>bswapsi2<setcc><setnz><setnzvc>"): Rename from "bswapsi2". ("*uminsi3<setcc><setnz><setnzvc>"): Rename from "*uminsi3".
2020-05-09cris: Enable general "and", "or", "xor", "not" to set condition codes.Hans-Peter Nilsson
Enabling dropping of compares with zero of the result, through any CCmode substitution. Beware that this will cause size-suboptimal operands to appear for e.g. 32-bit "and": -65536, -256, 255, 65535; for 16-bit "and" -256, -31..-1, 255; for 8-bit "and" -31..-1. Fixed for 0..31 for 16- and 8-bit sizes as it seemed worthwhile and used in libgcc. gcc: * config/cris/cris.md ("*expanded_andsi<setcc><setnz><setnzvc>"): Rename from "*expanded_andsi". ("*iorsi3<setcc><setnz><setnzvc>"): Similar from "*iorsi3". Decorate "cc" attribute to make "cc<cccc><ccnz><ccnzvc>". ("*iorhi3<setcc><setnz><setnzvc>"): Similar from "*iorhi3". ("*iorqi3<setcc><setnz><setnzvc>"): Similar from "*iorqi3". ("*expanded_andhi<setcc><setnz><setnzvc>"): Similar from "*expanded_andhi". Add quick cc-setting alternative for 0..31. ("*andqi3<setcc><setnz><setnzvc>"): Similar from "*andqi3". ("<acc><anz><anzvc>xorsi3<setcc><setnz><setnzvc>"): Rename from "xorsi3". ("<acc><anz><anzvc>one_cmplsi2<setcc><setnz><setnzvc>"): Rename from "one_cmplsi2".
2020-05-09cris: Enable additions and subtractions to set condition codes.Hans-Peter Nilsson
Enabling dropping of compares with zero of the result, through the non-VC-setting CCmode substitution. Beware that the substitutions for 8- and 16-bit patterns will in some cases be size-neutral; e.g. replacing an "addq 1..63,$rN" + "test.w $rN" or "subq 1..63,$rN" + "test.w $rN" with an "add.w -63..63,$rN". gcc: * config/cris/cris.md ("*adddi3<setnz>"): Rename from "*adddi3". cris: Enable 32-bit addition to set condition codes. ("*subdi3<setnz>"): Similarly from "*subdi3". ("*addsi3<setnz>"): Similarly from "*addsi3". ("*subsi3<setnz>"): Similarly from "*subsi3". ("*addhi3<setnz>"): Similarly from "*addhi3" and decorate the "cc" attribute to "cc<ccnz>". ("*addqi3<setnz>"): Similarly from "*addqi3". ("*sub<mode>3<setnz>"): Similarly from "*sub<mode>3".
2020-05-09cris: Enable extend operations to SImode to set condition codes.Hans-Peter Nilsson
Enable dropping of compares with zero of the result, through the three CCmode substitutions and the cmpelim pass. gcc: * config/cris/cris.md ("<acc><anz><anzvc>extend<mode>si2<setcc><setnz><setnzvc>"): Rename from "extend<mode>si2". ("<acc><anz><anzvc>zero_extend<mode>si2<setcc><setnz><setnzvc>"): Similar, from "zero_extend<mode>si2".
2020-05-09cris: Enable movhi and movqi to set condition codes. Anonymize.Hans-Peter Nilsson
Like with movsi_internal. Looks like the "cc" attribute didn't need tweaking for "movhi", but did for "movqi". N.B.: disabled alternatives make cause a later alternative to match. Also, non-anonymous insns get declarations and gen_* functions. We don't want that; even if it doesn't affect generated code it's sloppy. (This may or may not be preferable to the name decorations obfuscating standard pattern names.) Also anonymize left-over non-anonymous branches; they haven't been needing names since the cbranch pattern was made the generic method. gcc: * config/cris/cris.md ("anz", "anzvc", "acc"): New define_subst_attrs. ("<acc><anz><anzvc>movhi<setcc><setnz><setnzvc>"): Rename from "movhi". Rename "cc" attribute to "cc<cccc><ccnz><ccnzvc>". ("<acc><anz><anzvc>movqi<setcc><setnz><setnzvc>"): Similar from "movqi". Correct contents of, and rename "cc" attribute to "cc<cccc><ccnz><ccnzvc>". ("*b<zcond:code><mode>"): Rename from "b<zcond:code><mode>". ("*b<nzvccond:code><mode>"): Rename from "b<nzvccond:code><mode>". ("*b<rnzcond:code><mode>"): Rename from "*b<rnzcond:code><mode>".
2020-05-09cris: Enable *movsi_internal to set condition codes.Hans-Peter Nilsson
Completion of, and first use of, the CRIS-specific parts of the condition-code-setting framework, making use of the define_subst machinery and the cmpelim optimization pass. This round, just moves in SImode. Note the re-use of the cc0 era "cc" attribute (tweaks needed). gcc: * config/cris/cris.md ("cc"): Comment on new use. ("cc_enabled"): New attribute. ("enabled"): Make default fall back to cc_enabled. ("setnz", "ccnz", "setnzvc", "ccnzvc", "setcc", "cccc"): New default_subst_attrs. ("setnz_subst", "setnzvc_subst", "setcc_subst"): New default_subst. ("*movsi_internal<setcc><setnz><setnzvc>"): Rename from "*movsi_internal". Correct contents of, and rename attribute "cc" to "cc<cccc><ccnz><ccnzvc>".
2020-05-09cris: Introduce CC_NZVCmode and CC_NZmode.Hans-Peter Nilsson
This is just the framework bits of splitting CCmode into classes where the cc-setter can merge mode (CCmode), classes where the cc-setter must set V and C "usefully" (as well as N and Z flags) and classes where the cc-setter is something like an arithmetic instruction, where N and Z are valid but C and V reflect the operation rather than a compare of the result with zero. This should yield identical or near-identical code. The old split of conditions into the ncond and ocond sets took into account the transformations done by final.c:alter_cond from cc_status.flags & CC_NO_OVERFLOW, and wasn't a reflection of the hardware description of the conditions (i.e. whether V mattered or not). gcc: Prepare for cmpelim pass to eliminate redundant compare insns. * config/cris/cris-modes.def: New file. * config/cris/cris-protos.h (cris_select_cc_mode): Declare. (cris_notice_update_cc): Remove left-over declaration. * config/cris/cris.c (TARGET_CC_MODES_COMPATIBLE): Define. (cris_select_cc_mode, cris_cc_modes_compatible): New functions. * config/cris/cris.h (SELECT_CC_MODE): Define. * config/cris/cris.md (NZSET, NZUSE, NZVCSET, NZVCUSE): New mode_iterators. (cond): New code_iterator. (nzcond): Replacement for incorrect ncond. All callers changed. (nzvccond): Replacement for ocond. All callers changed. (rnzcond): Replacement for rcond. All callers changed. (xCC): New code_attr. (cmp_op1c, cmp_op0c): Renumber from cmp_op1c and cmp_op2c. All users changed. ("*cmpdi<NZVCSET:mode>"): Rename from "*cmpdi". Replace CCmode with iteration over NZVCSET. ("*cmp_ext<BW:mode><NZVCSET:mode>"): Similarly; rename from "*cmp_ext<mode>". ("*cmpsi<NZVCSET:mode>"): Similarly, from "*cmpsi". ("*cmp<BW:mode><NZVCSET:mode>"): Similarly from "*cmp<mode>". ("*btst<mode>"): Similarly, from "*btst". ("*cbranch<mode><code>4"): Rename from "*cbranch<mode>4", iterating over cond instead of matching the comparison with ordered_comparison_operator. ("*cbranch<mode>4_btstq<CC>"): Correct label operand number. ("b<zcond:code><mode>"): Rename from "b<ncond:code>", iterating over NZUSE. ("b<nzvccond:code><mode>"): Similarly from "b<ocond:code>", over NZVCUSE. Remove FIXME. ("*b<nzcond:code>_reversed<mode>"): Similarly from "*b<ncond:code>_reversed", over NZUSE. ("*b<nzvccond:code>_reversed<mode>"): Similarly from "*b<ocond:code>_reversed", over NZVCUSE. Remove FIXME. ("b<rnzcond:code><mode>"): Similarly from "b<rcond:code>", over NZUSE. Reinstate "b<oCC>" vs. "b<CC>" mnemonic choice, depending on CC_NZmode vs. CCmode. Remove FIXME. ("*b<rnzcond:code>_reversed<mode>"): Similarly from "*b<rcond:code>_reversed", over NZUSE. ("*cstore<mode><code>4"): Rename from "*cstore<mode>4", iterating over cond instead of matching the comparison with ordered_comparison_operator. ("*s<nzcond:code><mode>"): Rename from "*s<ncond:code>", iterating over NZUSE. ("*s<rnzcond:code><mode>"): Similar from "*s<rcond:code>", over NZUSE. Reinstate "b<oCC>" vs. "b<CC>" mnemonic choice, depending on CC_NZmode vs. CCmode. ("*s<nzvccond:code><mode>"): Simlar from "*s<ocond:code>", over NZVCUSE. Remove FIXME.
2020-05-09cris.md: Post-reload, split/generate clobberless zero source movesHans-Peter Nilsson
A separated follow-up to the previous change: Also emit moves from zero as not clobbering condition-codes. (note: actually folded into the previous ChangeLog-entry) gcc: * config/cris/cris.md ("movsi"): For a zero-source post-reload, generate a clobberless variant. ("*mov_fromzero<mode>_split"): New split. ("*mov_fromzero<mode>"): New insn.
2020-05-09cris.md: Post-reload, split/generate clobberless memory destination movesHans-Peter Nilsson
In preparation for compare-elimination (for it to be obviously useful), we have to have some common insn in-between that doesn't clobber condition-codes. A move to memory is an obvious choice. Note the FIXME: we can do this for a zero source too; later. gcc: * config/cris/cris.md ("movsi"): For memory destination post-reload, generate clobberless variant. ("*mov_tomem<mode>_split"): New split. ("*mov_tomem<mode>"): New insn. ("enabled", mov_tomem_enabled): Define and use to exclude "x" -> "Q>m" for less-than-SImode.
2020-05-09config/cris/cris.h (REVERSIBLE_CC_MODE): Define to true.Hans-Peter Nilsson
For some reason (like a buglet in the user in jump.c), defining this makes a beneficial difference in ledf2, thus this is separated to its own commit. Also, add comment on (not defining) REVERSE_CONDITION. gcc: * config/cris/cris.h (REVERSIBLE_CC_MODE): Define to true.
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