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2020-06-02amdgcn: Remove -mlocal-symbol-id optionAndrew Stubbs
This patch removes the obsolete -mlocal-symbol-id option. This was used to control mangling of local symbol names in order to work around a ROCm runtime bug, but that has not been needed in some time, and the mangling was removed already. gcc/ChangeLog: * config/gcn/gcn-hsa.h (CC1_SPEC): Delete. * config/gcn/gcn.opt (-mlocal-symbol-id): Delete. * config/gcn/mkoffload.c (main): Don't use -mlocal-symbol-id. gcc/testsuite/ChangeLog: * gcc.dg/intermod-1.c: Don't use -mlocal-symbol-id.
2020-05-29amdgcn: Fix VCC early clobberAndrew Stubbs
gcc/ChangeLog: 2020-05-28 Andrew Stubbs <ams@codesourcery.com> * config/gcn/gcn-valu.md (add<mode>3_vcc_zext_dup): Add early clobber. (add<mode>3_vcc_zext_dup_exec): Likewise. (add<mode>3_vcc_zext_dup2): Likewise. (add<mode>3_vcc_zext_dup2_exec): Likewise.
2020-05-15WIP amdgcn: use unsigned extend for lshiftrtAndrew Stubbs
This fixes a wrong-code logic error in a previous patch. Detected by gcc.c-torture/execute/pr53645-2.c. 2020-05-15 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (v<expander><mode>3): Fix unsignedp.
2020-05-14amdgcn: fix vcc clobber in vector load/storeAndrew Stubbs
This switches the code that expands scalar addresses to vectors of addresses from using VCC to using CC_SAVE_REG, for the lo-part to hi-part carry values. These were fine in code expanded in earlier passes, but addresses expanded late, such as for stack spills or reloads, could clobber live VCC values, causing execution failures. This is the first target-specific testcase for GCN, so the new .exp file is included. 2020-05-14 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (add<mode>3_zext_dup): Change to a define_expand, and rename the original to ... (add<mode>3_vcc_zext_dup): ... this, and add a custom VCC operand. (add<mode>3_zext_dup_exec): Likewise, with ... (add<mode>3_vcc_zext_dup_exec): ... this. (add<mode>3_zext_dup2): Likewise, with ... (add<mode>3_zext_dup_exec): ... this. (add<mode>3_zext_dup2_exec): Likewise, with ... (add<mode>3_zext_dup2): ... this. * config/gcn/gcn.c (gcn_expand_scalar_to_vector_address): Switch addv64di3_zext* calls to use addv64di3_vcc_zext*. gcc/testsuite/ * testsuite/gcc.target/gcn/gcn.exp: New file. * testsuite/gcc.target/gcn/vcc-clobber.c: New file.
2020-04-29[gcn] Fix build with RTL checking [PR94248]Jakub Jelinek
Building (for offloading) a '--target=amdgcn-amdhsa' GCC with '--enable-checking=yes,extra,rtl' fails: during RTL pass: split2 [...]/source-gcc/libgcc/libgcc2.c: In function '__absvdi2': [...]/source-gcc/libgcc/libgcc2.c:271:1: internal compiler error: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1923 271 | } | ^ 0x565847 ??? [...]/source-gcc/gcc/rtl.c:881 0x59a8a4 ??? [...]/source-gcc/gcc/rtl.h:1923 0x12e3a5c ??? [...]/source-gcc/gcc/config/gcn/gcn.md:631 [...] Makefile:501: recipe for target '_absvdi2.o' failed make[4]: *** [_absvdi2.o] Error 1 make[4]: Leaving directory '[...]/build-gcc-offload-amdgcn-amdhsa/amdgcn-amdhsa/gfx900/libgcc' gcc/ PR target/94248 * config/gcn/gcn.md (*mov<mode>_insn): Use 'reg_overlap_mentioned_p' to check for overlap. Tested-by: Thomas Schwinge <thomas@codesourcery.com>
2020-04-24amdgcn: Fix wrong-code bug in 64-bit masked addAndrew Stubbs
2020-04-24 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (add<mode>_zext_dup2_exec): Fix merge of high-part. (add<mode>_sext_dup2_exec): Likewise.
2020-04-24amdgcn: Split 64-bit constant loads post-reloadAndrew Stubbs
This helps avoid spilling 64-bit constant loads to stack by simplifying the code that LRA sees. 2020-04-24 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn.md (*mov<mode>_insn): Only split post-reload.
2020-04-23amdgcn: Swap mov<mode>_exec operandsAndrew Stubbs
Every other *_exec insn has the exec operand last. This being the other way around is a cause of bugs, and prevents use in macro templates. 2020-04-23 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (mov<mode>_exec): Swap the numbers on operands 2 and 3. (mov<mode>_exec): Likewise. (trunc<vndi><mode>2_exec): Swap parameters to gen_mov<mode>_exec. (<convop><mode><vndi>2_exec): Likewise.
2020-04-03amdgcn: Support unordered floating-point comparison operatorsKwok Cheung Yeung
2020-04-03 Kwok Cheung Yeung <kcy@codesourcery.com> gcc/ * config/gcn/gcn.c (print_operand): Handle unordered comparison operators. * config/gcn/predicates.md (gcn_fp_compare_operator): Add unordered comparison operators.
2020-03-31amdgcn: generalize vector insn modesAndrew Stubbs
Replace all relevant explicit uses of V64 vectors with an iterator (albeit with only one entry). This is prerequisite to adding extra vector lengths. The changes are purely mechanical: comparing the mddump files from before and after shows only white-space differences and the use of GET_MODE_NUNITS. 2020-03-31 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF): New mode iterators. (vnsi, VnSI, vndi, VnDI): New mode attributes. (mov<mode>): Use <VnDI> in place of V64DI. (mov<mode>_exec): Likewise. (mov<mode>_sgprbase): Likewise. (reload_out<mode>): Likewise. (*vec_set<mode>_1): Use GET_MODE_NUNITS instead of constant 64. (gather_load<mode>v64si): Rename to ... (gather_load<mode><vnsi>): ... this, and use <VnSI> in place of V64SI, and <VnDI> in place of V64DI. (gather<mode>_insn_1offset<exec>): Use <VnDI> in place of V64DI. (gather<mode>_insn_1offset_ds<exec>): Use <VnSI> in place of V64SI. (gather<mode>_insn_2offsets<exec>): Use <VnSI> and <VnDI>. (scatter_store<mode>v64si): Rename to ... (scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>. (scatter<mode>_expr<exec_scatter>): Use <VnSI> and <VnDI>. (scatter<mode>_insn_1offset<exec_scatter>): Likewise. (scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise. (scatter<mode>_insn_2offsets<exec_scatter>): Likewise. (ds_bpermute<mode>): Use <VnSI>. (addv64si3_vcc<exec_vcc>): Rename to ... (add<mode>3_vcc<exec_vcc>): ... this, and use V_SI. (addv64si3_vcc_dup<exec_vcc>): Rename to ... (add<mode>3_vcc_dup<exec_vcc>): ... this, and use V_SI. (addcv64si3<exec_vcc>): Rename to ... (addc<mode>3<exec_vcc>): ... this, and use V_SI. (subv64si3_vcc<exec_vcc>): Rename to ... (sub<mode>3_vcc<exec_vcc>): ... this, and use V_SI. (subcv64si3<exec_vcc>): Rename to ... (subc<mode>3<exec_vcc>): ... this, and use V_SI. (addv64di3): Rename to ... (add<mode>3): ... this, and use V_DI. (addv64di3_exec): Rename to ... (add<mode>3_exec): ... this, and use V_DI. (subv64di3): Rename to ... (sub<mode>3): ... this, and use V_DI. (subv64di3_exec): Rename to ... (sub<mode>3_exec): ... this, and use V_DI. (addv64di3_zext): Rename to ... (add<mode>3_zext): ... this, and use V_DI and <VnSI>. (addv64di3_zext_exec): Rename to ... (add<mode>3_zext_exec): ... this, and use V_DI and <VnSI>. (addv64di3_zext_dup): Rename to ... (add<mode>3_zext_dup): ... this, and use V_DI and <VnSI>. (addv64di3_zext_dup_exec): Rename to ... (add<mode>3_zext_dup_exec): ... this, and use V_DI and <VnSI>. (addv64di3_zext_dup2): Rename to ... (add<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>. (addv64di3_zext_dup2_exec): Rename to ... (add<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>. (addv64di3_sext_dup2): Rename to ... (add<mode>3_sext_dup2): ... this, and use V_DI and <VnSI>. (addv64di3_sext_dup2_exec): Rename to ... (add<mode>3_sext_dup2_exec): ... this, and use V_DI and <VnSI>. (<su>mulv64si3_highpart<exec>): Rename to ... (<su>mul<mode>3_highpart<exec>): ... this and use V_SI and <VnDI>. (mulv64di3): Rename to ... (mul<mode>3): ... this, and use V_DI and <VnSI>. (mulv64di3_exec): Rename to ... (mul<mode>3_exec): ... this, and use V_DI and <VnSI>. (mulv64di3_zext): Rename to ... (mul<mode>3_zext): ... this, and use V_DI and <VnSI>. (mulv64di3_zext_exec): Rename to ... (mul<mode>3_zext_exec): ... this, and use V_DI and <VnSI>. (mulv64di3_zext_dup2): Rename to ... (mul<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>. (mulv64di3_zext_dup2_exec): Rename to ... (mul<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>. (<expander>v64di3): Rename to ... (<expander><mode>3): ... this, and use V_DI and <VnSI>. (<expander>v64di3_exec): Rename to ... (<expander><mode>3_exec): ... this, and use V_DI and <VnSI>. (<expander>v64si3<exec>): Rename to ... (<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>. (v<expander>v64si3<exec>): Rename to ... (v<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>. (<expander>v64si3<exec>): Rename to ... (<expander><vnsi>3<exec>): ... this, and use V_SI. (subv64df3<exec>): Rename to ... (sub<mode>3<exec>): ... this, and use V_DF. (truncv64di<mode>2): Rename to ... (trunc<vndi><mode>2): ... this, and use <VnDI>. (truncv64di<mode>2_exec): Rename to ... (trunc<vndi><mode>2_exec): ... this, and use <VnDI>. (<convop><mode>v64di2): Rename to ... (<convop><mode><vndi>2): ... this, and use <VnDI>. (<convop><mode>v64di2_exec): Rename to ... (<convop><mode><vndi>2_exec): ... this, and use <VnDI>. (vec_cmp<u>v64qidi): Rename to ... (vec_cmp<u><mode>di): ... this, and use <VnSI>. (vec_cmp<u>v64qidi_exec): Rename to ... (vec_cmp<u><mode>di_exec): ... this, and use <VnSI>. (vcond_mask_<mode>di): Use <VnDI>. (maskload<mode>di): Likewise. (maskstore<mode>di): Likewise. (mask_gather_load<mode>v64si): Rename to ... (mask_gather_load<mode><vnsi>): ... this, and use <VnSI> and <VnDI>. (mask_scatter_store<mode>v64si): Rename to ... (mask_scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>. (*<reduc_op>_dpp_shr_v64di): Rename to ... (*<reduc_op>_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>. (*plus_carry_in_dpp_shr_v64si): Rename to ... (*plus_carry_in_dpp_shr_<mode>): ... this, and use V_SI. (*plus_carry_dpp_shr_v64di): Rename to ... (*plus_carry_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>. (vec_seriesv64si): Rename to ... (vec_series<mode>): ... this, and use V_SI. (vec_seriesv64di): Rename to ... (vec_series<mode>): ... this, and use V_DI.
2020-03-27amdgcn: refactor mode iteratorsAndrew Stubbs
The iterative addition of 8 and 16 bit vectors has left the mode iterators in a bit of a mess. Also, the original names were rather verbose leading to formatting difficulties. This patch renames all the vector modes such that they are shorter and tidier. It does not change the output machine description at all. 2020-03-27 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md: (VEC_SUBDWORD_MODE): Rename to V_QIHI throughout. (VEC_1REG_MODE): Delete. (VEC_1REG_ALT): Delete. (VEC_ALL1REG_MODE): Rename to V_1REG throughout. (VEC_1REG_INT_MODE): Delete. (VEC_ALL1REG_INT_MODE): Rename to V_INT_1REG throughout. (VEC_ALL1REG_INT_ALT): Rename to V_INT_1REG_ALT throughout. (VEC_2REG_MODE): Rename to V_2REG throughout. (VEC_REG_MODE): Rename to V_noHI throughout. (VEC_ALLREG_MODE): Rename to V_ALL throughout. (VEC_ALLREG_ALT): Rename to V_ALL_ALT throughout. (VEC_ALLREG_INT_MODE): Rename to V_INT throughout. (VEC_INT_MODE): Delete. (VEC_FP_MODE): Rename to V_FP throughout and move to top. (VEC_FP_1REG_MODE): Rename to V_FP_1REG throughout and move to top. (FP_MODE): Delete and replace with FP throughout. (FP_1REG_MODE): Delete and replace with FP_1REG throughout. (VCMP_MODE): Rename to V_noQI throughout and move to top. (VCMP_MODE_INT): Rename to V_INT_noQI throughout and move to top. * config/gcn/gcn.md (FP): New mode iterator. (FP_1REG): New mode iterator.
2020-03-18amdgcn: Fix vector compare modesAndrew Stubbs
The GCN VCC register has 64 CC values in one registers, one bit for each vector lane. Previously we avoided problems with invalid optimizations by not declaring a mode for the comparison operators, but it turns out that causes other problems (and build warnings). Instead, the optimization issues can be avoided by setting STORE_REGISTER_VALUE to -1, meaning that all the bits are significant. (It would be better if we could set STORE_REGISTER_VALUE according to the known mask or vector size, but we can't.) 2020-03-18 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (vec_cmp<mode>di): Set operand 1 to DImode. (vec_cmp<mode>di_dup): Likewise. * config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1.
2020-03-18amdgcn: Add cond_add/sub/and/ior/xor for all vector modesAndrew Stubbs
2020-03-18 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (COND_MODE): Delete. (COND_INT_MODE): Delete. (cond_op): Add "mult". (cond_<expander><mode>): Use VEC_ALLREG_MODE. (cond_<expander><mode>): Use VEC_ALLREG_INT_MODE.
2020-03-17Fix up duplicated duplicated words mostly in commentsJakub Jelinek
In the r10-7197-gbae7b38cf8a21e068ad5c0bab089dedb78af3346 commit I've noticed duplicated word in a message, which lead me to grep for those and we have a tons of them. I've used grep -v 'long long\|optab optab\|template template\|double double' *.[chS] */*.[chS] *.def config/*/* 2>/dev/null | grep ' \([a-zA-Z]\+\) \1 ' Note, the command will not detect the doubled words at the start or end of line or when one of the words is at the end of line and the next one at the start of another one. Some of it is fairly obvious, e.g. all the "the the" cases which is something I've posted and committed patch for already e.g. in 2016, other cases are often valid, e.g. "that that" seems to look mostly ok to me. Some cases are quite hard to figure out, I've left out some of them from the patch (e.g. "and and" in some cases isn't talking about bitwise/logical and and so looks incorrect, but in other cases it is talking about those operations). In most cases the right solution seems to be to remove one of the duplicated words, but not always. I think most important are the ones with user visible messages (in the patch 3 of the first 4 hunks), the rest is just comments (and internal documentation; for that see the doc/tm.texi changes). 2020-03-17 Jakub Jelinek <jakub@redhat.com> * lra-spills.c (remove_pseudos): Fix up duplicated word issue in a dump message. * tree-sra.c (create_access_replacement): Fix up duplicated word issue in a comment. * read-rtl-function.c (find_param_by_name, function_reader::parse_enum_value, function_reader::get_insn_by_uid): Likewise. * spellcheck.c (get_edit_distance_cutoff): Likewise. * tree-data-ref.c (create_ifn_alias_checks): Likewise. * tree.def (SWITCH_EXPR): Likewise. * selftest.c (assert_str_contains): Likewise. * ipa-param-manipulation.h (class ipa_param_body_adjustments): Likewise. * tree-ssa-math-opts.c (convert_expand_mult_copysign): Likewise. * tree-ssa-loop-split.c (find_vdef_in_loop): Likewise. * langhooks.h (struct lang_hooks_for_decls): Likewise. * ipa-prop.h (struct ipa_param_descriptor): Likewise. * tree-ssa-strlen.c (handle_builtin_string_cmp, handle_store): Likewise. * tree-ssa-dom.c (simplify_stmt_for_jump_threading): Likewise. * tree-ssa-reassoc.c (reassociate_bb): Likewise. * tree.c (component_ref_size): Likewise. * hsa-common.c (hsa_init_compilation_unit_data): Likewise. * gimple-ssa-sprintf.c (get_string_length, format_string, format_directive): Likewise. * omp-grid.c (grid_process_kernel_body_copy): Likewise. * input.c (string_concat_db::get_string_concatenation, test_lexer_string_locations_ucn4): Likewise. * cfgexpand.c (pass_expand::execute): Likewise. * gimple-ssa-warn-restrict.c (builtin_memref::offset_out_of_bounds, maybe_diag_overlap): Likewise. * rtl.c (RTX_CODE_HWINT_P_1): Likewise. * shrink-wrap.c (spread_components): Likewise. * tree-ssa-dse.c (initialize_ao_ref_for_dse, valid_ao_ref_for_dse): Likewise. * tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds): Likewise. * dwarf2out.c (dwarf2out_early_finish): Likewise. * gimple-ssa-store-merging.c: Likewise. * ira-costs.c (record_operand_costs): Likewise. * tree-vect-loop.c (vectorizable_reduction): Likewise. * target.def (dispatch): Likewise. (validate_dims, gen_ccmp_first): Fix up duplicated word issue in documentation text. * doc/tm.texi: Regenerated. * config/i386/x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Fix up duplicated word issue in a comment. * config/i386/i386.c (ix86_test_loading_unspec): Likewise. * config/i386/i386-features.c (remove_partial_avx_dependency): Likewise. * config/msp430/msp430.c (msp430_select_section): Likewise. * config/gcn/gcn-run.c (load_image): Likewise. * config/aarch64/aarch64-sve.md (sve_ld1r<mode>): Likewise. * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Likewise. * config/aarch64/falkor-tag-collision-avoidance.c (single_dest_per_chain): Likewise. * config/nvptx/nvptx.c (nvptx_record_fndecl): Likewise. * config/fr30/fr30.c (fr30_arg_partial_bytes): Likewise. * config/rs6000/rs6000-string.c (expand_cmp_vec_sequence): Likewise. * config/rs6000/rs6000-p8swap.c (replace_swapped_load_constant): Likewise. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise. * config/rs6000/rs6000.c (rs6000_option_override_internal): Likewise. * config/rs6000/rs6000-logue.c (rs6000_emit_probe_stack_range_stack_clash): Likewise. * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Likewise. Fix various other issues in the comment. c-family/ * c-common.c (resolve_overloaded_builtin): Fix up duplicated word issue in a diagnostic message. cp/ * pt.c (tsubst): Fix up duplicated word issue in a diagnostic message. (lookup_template_class_1, tsubst_expr): Fix up duplicated word issue in a comment. * parser.c (cp_parser_statement, cp_parser_linkage_specification, cp_parser_placeholder_type_specifier, cp_parser_constraint_requires_parens): Likewise. * name-lookup.c (suggest_alternative_in_explicit_scope): Likewise. fortran/ * array.c (gfc_check_iter_variable): Fix up duplicated word issue in a comment. * arith.c (gfc_arith_concat): Likewise. * resolve.c (gfc_resolve_ref): Likewise. * frontend-passes.c (matmul_lhs_realloc): Likewise. * module.c (gfc_match_submodule, load_needed): Likewise. * trans-expr.c (gfc_init_se): Likewise.
2020-03-02amdgcn: Extend reductions to all typesAndrew Stubbs
Add support for V64DFmode addition, and V64DImode min, max. There's no direct hardware support for these, so we use regular vector instructions and separate lane shift instructions. Also add support for V64QI and V64HI reductions. Some of these require additional extends and truncates, because AMD GCN has 32-bit vector lanes. 2020-03-02 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (dpp_move<mode>): New. (reduc_insn): Use 'U' and 'B' operand codes. (reduc_<reduc_op>_scal_<mode>): Allow all types. (reduc_<reduc_op>_scal_v64di): Delete. (*<reduc_op>_dpp_shr_<mode>): Allow all 1reg types. (*plus_carry_dpp_shr_v64si): Change to ... (*plus_carry_dpp_shr_<mode>): ... this and allow all 1reg int types. (mov_from_lane63_v64di): Change to ... (mov_from_lane63_<mode>): ... this, and allow all 64-bit modes. * config/gcn/gcn.c (gcn_expand_dpp_shr_insn): Increase buffer size. Support UNSPEC_MOV_DPP_SHR output formats. (gcn_expand_reduc_scalar): Add "use_moves" reductions. Add "use_extends" reductions. (print_operand_address): Add 'I' and 'U' codes. * config/gcn/gcn.md (unspec): Add UNSPEC_MOV_DPP_SHR.
2020-02-27amdgcn: sub-dword vector min/max/shift/bit operatorsAndrew Stubbs
2020-02-27 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (VEC_SUBDWORD_MODE): New mode iterator. (<expander><mode>2<exec>): Change modes to VEC_ALL1REG_INT_MODE. (<expander><mode>3<exec>): Likewise. (<expander><mode>3): New. (v<expander><mode>3): New. (<expander><mode>3): New. (<expander><mode>3<exec>): Rename to ... (<expander>v64si3<exec>): ... this, and change modes to V64SI. * config/gcn/gcn.md (mnemonic): Use '%B' for not.
2020-02-27amdgcn: fix ICE on subreg of BI reg.Andrew Stubbs
BImode usually only requires one bit, but instructions that write to VCC also clobber the reset of the DImode register pair, so gcn_class_max_nregs reports that two registers are needed for BImode. Paradoxically, accessing VCC via SImode is therefore uses fewer registers than accessing via BImode. The LRA checking code takes this into account, but the DF liveness data also looks at the subreg, so it says (subreg:SI (reg:BI VCC) 0) only makes the low part live. Both are "correct", but they disagree, which causes an ICE. This doesn't happen when writing conditions to VCC; it happens when accessing VCC_LO via a regular move to a regular SImode register. If we transform the subregs so that BImode is always the outer mode then it basically means the same thing, except that now both LRA and DF calculate nregs the same, and ICE goes away. As soon as LRA is done the subregs all evaporate anyway. 2020-02-27 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn.md (mov<mode>): Add transformations for BI subregs.
2020-02-21amdgcn: Use correct offset mode for gather/scatterAndrew Stubbs
The scatter/gather pattern names changed for GCC 10, but I hadn't noticed. This switches the patterns to the new offset mode scheme. 2020-02-21 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (gather_load<mode>): Rename to ... (gather_load<mode>v64si): ... this and set operand 2 to V64SI. (scatter_store<mode>): Rename to ... (scatter_store<mode>v64si): ... this and set operand 1 to V64SI. (scatter<mode>_exec): Delete. Move contents ... (mask_scatter_store<mode>): ... here, and rename that to ... (mask_gather_load<mode>v64si): ... this. Set operand 2 to V64SI. Remove mode conversion. (mask_gather_load<mode>): Rename to ... (mask_scatter_store<mode>v64si): ... this. Set operand 1 to V64SI. Remove mode conversion. * config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion.
2020-02-21amdgcn: Align VGPR pairsAndrew Stubbs
Aligning the registers is not needed by the architecture, but doing so allows us to remove the requirement for bug-prone early-clobber constraints from many split patterns (and avoid adding more in future). 2020-02-21 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align VGPR pairs. * config/gcn/gcn-valu.md (addv64di3): Remove early-clobber. (addv64di3_exec): Likewise. (subv64di3): Likewise. (subv64di3_exec): Likewise. (addv64di3_zext): Likewise. (addv64di3_zext_exec): Likewise. (addv64di3_zext_dup): Likewise. (addv64di3_zext_dup_exec): Likewise. (addv64di3_zext_dup2): Likewise. (addv64di3_zext_dup2_exec): Likewise. (addv64di3_sext_dup2): Likewise. (addv64di3_sext_dup2_exec): Likewise. (<expander>v64di3): Likewise. (<expander>v64di3_exec): Likewise. (*<reduc_op>_dpp_shr_v64di): Likewise. (*plus_carry_dpp_shr_v64di): Likewise. * config/gcn/gcn.md (adddi3): Likewise. (addptrdi3): Likewise. (<expander>di3): Likewise.
2020-02-21amdgcn: fix mode in vec_seriesAndrew Stubbs
2020-02-21 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (vec_seriesv64di): Use gen_vec_duplicatev64di.
2020-02-05amdgcn: Remove redundant multilibAndrew Stubbs
2020-02-05 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/t-gcn-hsa (MULTILIB_OPTIONS): Use / not space.
2020-02-03Remove gfx801 "carrizo" supportAndrew Stubbs
2020-02-03 Andrew Stubbs <ams@codesourcery.com> gcc/ * config.gcc: Remove "carrizo" support. * config/gcn/gcn-opts.h (processor_type): Likewise. * config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Likewise. * config/gcn/gcn.opt (gpu_type): Likewise. * config/gcn/t-omp-device: Likewise. libgomp/ * plugin/plugin-gcn.c (EF_AMDGPU_MACH_AMDGCN_GFX801): Remove. (gcn_gfx801_s): Remove. (isa_hsa_name): Remove gfx801. (isa_gcc_name): Remove gfx801/carizzo. (isa_code): Remove gfx801.
2020-01-31Fix conditional add LRA failure for amdgcnAndrew Stubbs
Fix ICE in testcase gfortran.dg/assumed_rank_bounds_3.f90. 2020-01-31 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (addv64di3_exec): Allow one '0' in each alternative only.
2020-01-31[amdgcn] Scale number of threads/workers with VGPR usageKwok Cheung Yeung
2020-01-31 Kwok Cheung Yeung <kcy@codesourcery.com> gcc/ * config/gcn/mkoffload.c (process_asm): Add sgpr_count and vgpr_count to definition of hsa_kernel_description. Parse assembly to find SGPR and VGPR count of kernel and store in hsa_kernel_description. libgomp/ * plugin/plugin-gcn.c (struct hsa_kernel_description): Add sgpr_count and vgpr_count fields. (struct kernel_info): Add a field for a hsa_kernel_description. (run_kernel): Reduce the number of threads/workers if the requested number would require too many VGPRs. (init_basic_kernel_info): Initialize description field with the hsa_kernel_description entry for the kernel.
2020-01-31Zero-initialise masked load destinationsAndrew Stubbs
Fixes an execution failure in testcase gfortran.dg/assumed_rank_1.f90. 2020-01-30 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (gather<mode>_exec): Move contents ... (mask_gather_load<mode>): ... here, and zero-initialize the destination. (maskload<mode>di): Zero-initialize the destination. * config/gcn/gcn.c:
2020-01-30Add LTGT operator support for amdgcnAndrew Stubbs
Fixes ICE in testcase gcc.dg/pr81228.c 2020-01-30 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn.c (print_operand): Handle LTGT. * config/gcn/predicates.md (gcn_fp_compare_operator): Allow ltgt.
2020-01-29GCN – call assembler with -mattr=-code-object-v3 (PR93409)Tobias Burnus
PR bootstrap/93409 * config/gcn/gcn-hsa.h (ASM_SPEC): Add -mattr=-code-object-v3 as LLVM's assembler changed the default in version 9.
2020-01-24Fix ICE on unsupported FP comparisonAndrew Stubbs
2020-01-24 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (vec_cmp<mode>di): Use gcn_fp_compare_operator. (vec_cmpu<mode>di): Use gcn_compare_operator. (vec_cmp<u>v64qidi): Use gcn_compare_operator. (vec_cmp<mode>di_exec): Use gcn_fp_compare_operator. (vec_cmpu<mode>di_exec): Use gcn_compare_operator. (vec_cmp<u>v64qidi_exec): Use gcn_compare_operator. (vec_cmp<mode>di_dup): Use gcn_fp_compare_operator. (vec_cmp<mode>di_dup_exec): Use gcn_fp_compare_operator. (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): Use gcn_fp_compare_operator. (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): Use gcn_fp_compare_operator. (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): Use gcn_fp_compare_operator. (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): Use gcn_fp_compare_operator.
2020-01-07[amdgcn] Add more modes for vector comparisonsAndrew Stubbs
2020-01-07 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator. (VEC_ALLREG_ALT): New iterator. (VEC_ALLREG_INT_MODE): New iterator. (VCMP_MODE): New iterator. (VCMP_MODE_INT): New iterator. (vec_cmpu<mode>di): Use VCMP_MODE_INT. (vec_cmp<u>v64qidi): New define_expand. (vec_cmp<mode>di_exec): Use VCMP_MODE. (vec_cmpu<mode>di_exec): New define_expand. (vec_cmp<u>v64qidi_exec): New define_expand. (vec_cmp<mode>di_dup): Use VCMP_MODE. (vec_cmp<mode>di_dup_exec): Use VCMP_MODE. (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>): Rename ... (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): ... to this. (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Rename ... (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): ... to this. (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Rename ... (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): ... to this. (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Rename ... (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): ... to this. * config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes. * config/gcn/gcn.md (expander): Add sign_extend and zero_extend. From-SVN: r279961
2020-01-07Disallow 'B' constraints on amdgcn addc/subbAndrew Stubbs
2020-01-07 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/constraints.md (DA): Update description and match. (DB): Likewise. (Db): New constraint. * config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second parameter. * config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter. Implement 'Db' mixed immediate type. * config/gcn/gcn-valu.md (addcv64si3<exec_vcc>): Rework constraints. (addcv64si3_dup<exec_vcc>): Delete. (subcv64si3<exec_vcc>): Rework constraints. (addv64di3): Rework constraints. (addv64di3_exec): Rework constraints. (subv64di3): Rework constraints. (addv64di3_dup): Delete. (addv64di3_dup_exec): Delete. (addv64di3_zext): Rework constraints. (addv64di3_zext_exec): Rework constraints. (addv64di3_zext_dup): Rework constraints. (addv64di3_zext_dup_exec): Rework constraints. (addv64di3_zext_dup2): Rework constraints. (addv64di3_zext_dup2_exec): Rework constraints. (addv64di3_sext_dup2): Rework constraints. (addv64di3_sext_dup2_exec): Rework constraints. From-SVN: r279959
2020-01-06Fix amdgcn issue with '0' constraintsAndrew Stubbs
2020-01-06 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for '0' matching inputs. (subv64di3_exec): Likewise. From-SVN: r279906
2020-01-06Fix early-clobber in amdgcn vec_extractAndrew Stubbs
2020-01-06 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early clobber. From-SVN: r279904
2020-01-06Fix amdgcn inline immediate rangeAndrew Stubbs
2020-01-06 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline immediate. From-SVN: r279898
2020-01-01Update copyright years.Jakub Jelinek
From-SVN: r279813
2019-12-19Allow constants in amdgcn extends and truncatesAndrew Stubbs
2019-12-19 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (<convop><VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>): Change input predcate to gcn_alu_operand. (extend<VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>): Likewise. (truncv64di<mode>2): Likewise. (truncv64di<mode>2_exec): Likewise. (<convop><mode>v64di2): Likewise. (<convop><mode>v64di2_exec): Likewise. From-SVN: r279587
2019-12-19Use V64SI for all amdgcn add-with-carry insnsAndrew Stubbs
2019-12-19 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (*plus_carry_dpp_shr_<mode>): Rename to ... (*plus_carry_dpp_shr_v64si): ... this, and replace all VEC_1REG_INT_MODE with V64SI. From-SVN: r279584
2019-12-19Implement sub-dword add/sub on amdgcnAndrew Stubbs
2019-12-19 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (addv64si3<exec_clobber>): Rename to ... (add<mode>3<exec_clobber>): ... this, and use VEC_ALL1REG_INT_MODE. (addv64si3_dup<exec_clobber>): Rename to ... (add<mode>3_dup<exec_clobber>): ... this, and use VEC_ALL1REG_INT_MODE. (subv64si3<exec_clobber>): Rename to ... (sub<mode>3<exec_clobber>): ... this, and use VEC_ALL1REG_INT_MODE. From-SVN: r279574
2019-12-17Add extract_last for amdgcnAndrew Stubbs
2019-12-17 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (extract_last_<mode>): New expander. (fold_extract_last_<mode>): New expander. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_vect_fold_extract_last): Add amdgcn. From-SVN: r279459
2019-12-17Add clz and ctz for amdgcnAndrew Stubbs
2019-12-17 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn.h (CLZ_DEFINED_VALUE_AT_ZERO): Define. (CTZ_DEFINED_VALUE_AT_ZERO): Define. * config/gcn/gcn.md (s_mnemonic): Add clz and ctz. (expander): Likewise. (countzeros): New code iterator. (<expander>si2): New insn pattern. (<expander>di2): New insn pattern. From-SVN: r279458
2019-12-13Sub-dword vector multiply for amdgcnAndrew Stubbs
2019-12-13 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (mulv64si3<exec>): Rename to ... (mul<mode>3<exec>): ... this, and implement sub-dword patterns. (mulv64si3_dup<exec>): Rename to ... (mul<mode>3_dup<exec>): ... this, and implement sub-dword patterns. From-SVN: r279374
2019-12-13Sub-dword vector extend and truncate for amdgcnAndrew Stubbs
2019-12-13 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (sdwa): New mode attribute. (VCVT_FROM_MODE): Rename to ... (VCVT_MODE): ... this. (VCVT_TO_MODE): Delete mode iterator. (VCVT_FMODE): New mode iterator. (VCVT_IMODE): Likewise. (<cvt_name><VCVT_FROM_MODE:mode><VCVT_TO_MODE:mode>2<exec>): Change ... (<cvt_name><VCVT_MODE:mode><VCVT_FMODE:mode>2<exec>): ... to this. (<cvt_name><VCVT_FMODE:mode><VCVT_IMODE:mode>2<exec>): New. (zero_convert): New code iterator. (convop): New code attribute. (<convop><VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>) : New. (extend<VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>) : New. (vec_truncatev64div64si): Rename to ... (truncv64di<mode>2): ... this and implement sub-dword patterns. (vec_truncatev64div64si_exec): Rename to ... (truncv64di<mode>2_exec): ... this and implement sub-dword patterns. (<convop><mode>v64di2): New insn_and_split. (<convop><mode>v64di2_exec): Likewise. (mask_gather_load<mode>): Update truncate names. (mask_scatter_store<mode>): Likewise. * config/gcn/gcn.c (gcn_expand_scaled_offsets): Update truncate names. From-SVN: r279372
2019-12-09Fix more unrecognised GCN instructionsAndrew Stubbs
2019-12-09 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (gather<mode>_insn_1offset<exec>): Change %s to %o in asm output. (gather<mode>_insn_2offsets<exec>): Likewise. From-SVN: r279131
2019-12-06Fix unrecognised GCN instruction.Andrew Stubbs
2019-12-06 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (gather<mode>_insn_1offset<exec>): Use %o in the asm output. From-SVN: r279055
2019-12-06Enable QI/HImode vector movesAndrew Stubbs
2019-12-06 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (VEC_1REG_MODE): Remove V64QI and V64HI. (VEC_1REG_ALT): Likewise. (VEC_ALL1REG_MODE): New mode iterator. (VEC_1REG_INT_MODE): Remove V64QI and V64HI. (VEC_1REG_INT_ALT): Likewise. (VEC_ALL1REG_INT_MODE): New mode interator. (VEC_ALL1REG_INT_ALT): Likewise. (VEC_REG_MODE): Remove V64QI and V64HI. (VEC_ALLREG_MODE): New mode interator. (vec_merge): Change to VEC_ALLREG_MODE. (vec_merge_with_clobber): Likewise. (vec_merge_with_vcc): Likewise. (mov<mode>): Likewise. (mov<mode>_unspec): Likewise. (*mov<mode>): Change to VEC_ALL1REG_MODE. (mov<mode>_exec): Likewise. (*mov<mode>_exec_match): Likewise. (mov<mode>_sgprbase): Likewise. (reload_in<mode>): Change to VEC_ALLREG_MODE. (reload_out<mode>): Likewise. (scalar address splits): Likewise. (*vec_set<mode>): Change to VEC_ALL1REG_MODE. (vec_set<mode>): Change to VEC_ALLREG_MODE. (*vec_set<mode>_1): Change to VEC_ALL1REG_MODE. (vec_duplicate<mode><exec>): Likewise. (vec_extract<mode><scalar_mode>): Likewise. (vec_init<mode><scalar_mode>): Change to VEC_ALLREG_MODE. (gather_load<mode>): Likewise. (gather<mode>_exec): Likewise. (gather<mode>_expr<exec>): Likewise. (gather<mode>_insn_1offset<exec>): Likewise. (gather<mode>_insn_1offset_ds<exec>): Likewise. (gather<mode>_insn_2offsets<exec>): Likewise. (ds_bpermute<mode>): Change to VEC_ALL1REG_MODE. (VEC_INT_MODE): Remove V64QI and V64HI. (vcond_mask_<mode>di): Change to VEC_ALLREG_MODE. (vcond<VEC_1REG_MODE:mode><VEC_1REG_ALT:mode>): Change to VEC_ALL1REG_MODE. (vcond<VEC_1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Likewise. (vcondu<VEC_1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Likewise. (vcondu<VEC_1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Likewise. (maskload<mode>di): Change to VEC_ALL1REG_MODE. (maskstore<mode>di): Likewise. (mask_gather_load<mode>): Likewise. (mov_from_lane63_<mode>): Likewise. * config/gcn/gcn.c (gcn_vector_mode_supported_p): Renable V64QImode and V64HImode vectorization. (gcn_related_vector_mode): New function. (TARGET_VECTORIZE_RELATED_MODE): New define. From-SVN: r279053
2019-12-04Use fixed registers for queue ptr sgpr pairJulian Brown
gcc/ * config/gcn/gcn.h (FIXED_REGISTERS): Make s6/s7 fixed registers. From-SVN: r278974
2019-12-03Add missing amdgcn vcondu patternsAndrew Stubbs
2019-12-03 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md: Change "vcondu" patterns to use VEC_1REG_MODE for the data mode. From-SVN: r278940
2019-11-25config/gcn/mkoffload.c – remove unused static varsTobias Burnus
* config/gcn/mkoffload.c (COMMENT_PREFIX, struct id_map, func_ids, funcs_tail, var_ids, vars_tail) Remove unused definitions. From-SVN: r278688
2019-11-25[amdgcn] Silence warnings + add gcc_unreachable()Tobias Burnus
* config/gcn/gcn.c (gcn_expand_scalar_to_vector_address, gcn_md_reorg): Remove unused variables. (gcn_emutls_var_init): Add missing (but unreachable) return to silence warning. (gcn_hsa_declare_function_name): Add gcc_unreachable to ensure target != TARGET_GCN3 or TARGET_GCN3 will fail instead of use an uninitialized variable. From-SVN: r278678
2019-11-22Limit LDS usage.Andrew Stubbs
2019-11-22 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn.c (OMP_LDS_SIZE): Define. (ACC_LDS_SIZE): Define. (OTHER_LDS_SIZE): Define. (LDS_SIZE): Redefine using above. (gcn_expand_prologue): Initialize m0 with LDS_SIZE-1. From-SVN: r278622
2019-11-22Use GFX9 granulated sgprs count correctly.Andrew Stubbs
2019-11-22 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn.c (gcn_hsa_declare_function_name): Calculate granulated_sgprs according to architecture. From-SVN: r278617
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