diff options
| author | Segher Boessenkool <segher@kernel.crashing.org> | 2018-09-18 18:19:56 +0200 |
|---|---|---|
| committer | Segher Boessenkool <segher@gcc.gnu.org> | 2018-09-18 18:19:56 +0200 |
| commit | b7663a763fdeff95ffe2ea8d1ef46ad74c26491e (patch) | |
| tree | d3c357de4d00518720240c369368be7d6aab210c /gcc/rtlanal.c | |
| parent | a12c16de529755cdf4dbc594dd48742107ad349e (diff) | |
Handle CLOBBER in reg_overlap_mentioned_p (PR86882)
Combine will put CLOBBER (with a non-void mode) anywhere in a pattern
to poison it. reg_overlap_mentioned_p did not handle this. This patch
fixes that.
PR rtl-optimization/86882
* rtlanal.c (reg_overlap_mentioned_p): Handle CLOBBER.
From-SVN: r264400
Diffstat (limited to 'gcc/rtlanal.c')
| -rw-r--r-- | gcc/rtlanal.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index 6c620a4a3e5..366df7c9b3f 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -1815,6 +1815,7 @@ reg_overlap_mentioned_p (const_rtx x, const_rtx in) recurse: switch (GET_CODE (x)) { + case CLOBBER: case STRICT_LOW_PART: case ZERO_EXTRACT: case SIGN_EXTRACT: @@ -4757,17 +4758,17 @@ nonzero_bits1 (const_rtx x, scalar_int_mode mode, const_rtx known_x, nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode, known_x, known_mode, known_ret); - /* On many CISC machines, accessing an object in a wider mode + /* On many CISC machines, accessing an object in a wider mode causes the high-order bits to become undefined. So they are not known to be zero. */ rtx_code extend_op; if ((!WORD_REGISTER_OPERATIONS /* If this is a typical RISC machine, we only have to worry about the way loads are extended. */ + || !MEM_P (SUBREG_REG (x)) || ((extend_op = load_extend_op (inner_mode)) == SIGN_EXTEND ? val_signbit_known_set_p (inner_mode, nonzero) - : extend_op != ZERO_EXTEND) - || (!MEM_P (SUBREG_REG (x)) && !REG_P (SUBREG_REG (x)))) + : extend_op != ZERO_EXTEND)) && xmode_width > inner_width) nonzero |= (GET_MODE_MASK (GET_MODE (x)) & ~GET_MODE_MASK (inner_mode)); |