rs6000: Vector string isolate instructions

Adds new instructions vstribr, vstrihr, vstribl, and vstrihl, with
overloaded built-in support.

[gcc]

2020-05-11  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	* config/rs6000/altivec.h (vec_strir): New #define.
	(vec_stril): Likewise.
	(vec_strir_p): Likewise.
	(vec_stril_p): Likewise.
	* config/rs6000/altivec.md (UNSPEC_VSTRIR): New constant.
	(UNSPEC_VSTRIL): Likewise.
	(vstrir_<mode>): New expansion.
	(vstrir_code_<mode>): New insn.
	(vstrir_p_<mode>): New expansion.
	(vstrir_p_code_<mode>): New insn.
	(vstril_<mode>): New expansion.
	(vstril_code_<mode>): New insn.
	(vstril_p_<mode>): New expansion.
	(vstril_p_code_<mode>): New insn.
	* config/rs6000/rs6000-builtin.def (__builtin_altivec_vstribr):
	New built-in function.
	(__builtin_altivec_vstrihr): Likewise.
	(__builtin_altivec_vstribl): Likewise.
	(__builtin_altivec_vstrihl): Likewise.
	(__builtin_altivec_vstribr_p): Likewise.
	(__builtin_altivec_vstrihr_p): Likewise.
	(__builtin_altivec_vstribl_p): Likewise.
	(__builtin_altivec_vstrihl_p): Likewise.
	(__builtin_vec_strir): New overloaded built-in function.
	(__builtin_vec_stril): Likewise.
	(__builtin_vec_strir_p): Likewise.
	(__builtin_vec_stril_p): Likewise.
	* config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
	Define overloaded forms of __builtin_vec_strir,
	__builtin_vec_stril, __builtin_vec_strir_p, and
	__builtin_vec_stril_p.
	* doc/extend.texi (PowerPC AltiVec Built-in Functions Available
	for a Future Architecture): Add description of vec_stril,
	vec_stril_p, vec_strir, and vec_strir_p built-in functions.

[gcc]

2020-05-11  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	* gcc.target/powerpc/vec-stril-0.c: New.
	* gcc.target/powerpc/vec-stril-1.c: New.
	* gcc.target/powerpc/vec-stril-10.c: New.
	* gcc.target/powerpc/vec-stril-11.c: New.
	* gcc.target/powerpc/vec-stril-12.c: New.
	* gcc.target/powerpc/vec-stril-13.c: New.
	* gcc.target/powerpc/vec-stril-14.c: New.
	* gcc.target/powerpc/vec-stril-15.c: New.
	* gcc.target/powerpc/vec-stril-16.c: New.
	* gcc.target/powerpc/vec-stril-17.c: New.
	* gcc.target/powerpc/vec-stril-18.c: New.
	* gcc.target/powerpc/vec-stril-19.c: New.
	* gcc.target/powerpc/vec-stril-2.c: New.
	* gcc.target/powerpc/vec-stril-20.c: New.
	* gcc.target/powerpc/vec-stril-21.c: New.
	* gcc.target/powerpc/vec-stril-22.c: New.
	* gcc.target/powerpc/vec-stril-23.c: New.
	* gcc.target/powerpc/vec-stril-3.c: New.
	* gcc.target/powerpc/vec-stril-4.c: New.
	* gcc.target/powerpc/vec-stril-5.c: New.
	* gcc.target/powerpc/vec-stril-6.c: New.
	* gcc.target/powerpc/vec-stril-7.c: New.
	* gcc.target/powerpc/vec-stril-8.c: New.
	* gcc.target/powerpc/vec-stril-9.c: New.
	* gcc.target/powerpc/vec-stril_p-0.c: New.
	* gcc.target/powerpc/vec-stril_p-1.c: New.
	* gcc.target/powerpc/vec-stril_p-10.c: New.
	* gcc.target/powerpc/vec-stril_p-11.c: New.
	* gcc.target/powerpc/vec-stril_p-2.c: New.
	* gcc.target/powerpc/vec-stril_p-3.c: New.
	* gcc.target/powerpc/vec-stril_p-4.c: New.
	* gcc.target/powerpc/vec-stril_p-5.c: New.
	* gcc.target/powerpc/vec-stril_p-6.c: New.
	* gcc.target/powerpc/vec-stril_p-7.c: New.
	* gcc.target/powerpc/vec-stril_p-8.c: New.
	* gcc.target/powerpc/vec-stril_p-9.c: New.
	* gcc.target/powerpc/vec-strir-0.c: New.
	* gcc.target/powerpc/vec-strir-1.c: New.
	* gcc.target/powerpc/vec-strir-10.c: New.
	* gcc.target/powerpc/vec-strir-11.c: New.
	* gcc.target/powerpc/vec-strir-12.c: New.
	* gcc.target/powerpc/vec-strir-13.c: New.
	* gcc.target/powerpc/vec-strir-14.c: New.
	* gcc.target/powerpc/vec-strir-15.c: New.
	* gcc.target/powerpc/vec-strir-16.c: New.
	* gcc.target/powerpc/vec-strir-17.c: New.
	* gcc.target/powerpc/vec-strir-18.c: New.
	* gcc.target/powerpc/vec-strir-19.c: New.
	* gcc.target/powerpc/vec-strir-2.c: New.
	* gcc.target/powerpc/vec-strir-20.c: New.
	* gcc.target/powerpc/vec-strir-21.c: New.
	* gcc.target/powerpc/vec-strir-22.c: New.
	* gcc.target/powerpc/vec-strir-23.c: New.
	* gcc.target/powerpc/vec-strir-3.c: New.
	* gcc.target/powerpc/vec-strir-4.c: New.
	* gcc.target/powerpc/vec-strir-5.c: New.
	* gcc.target/powerpc/vec-strir-6.c: New.
	* gcc.target/powerpc/vec-strir-7.c: New.
	* gcc.target/powerpc/vec-strir-8.c: New.
	* gcc.target/powerpc/vec-strir-9.c: New.
	* gcc.target/powerpc/vec-strir_p-0.c: New.
	* gcc.target/powerpc/vec-strir_p-1.c: New.
	* gcc.target/powerpc/vec-strir_p-10.c: New.
	* gcc.target/powerpc/vec-strir_p-11.c: New.
	* gcc.target/powerpc/vec-strir_p-2.c: New.
	* gcc.target/powerpc/vec-strir_p-3.c: New.
	* gcc.target/powerpc/vec-strir_p-4.c: New.
	* gcc.target/powerpc/vec-strir_p-5.c: New.
	* gcc.target/powerpc/vec-strir_p-6.c: New.
	* gcc.target/powerpc/vec-strir_p-7.c: New.
	* gcc.target/powerpc/vec-strir_p-8.c: New.
	* gcc.target/powerpc/vec-strir_p-9.c: New.

1 files changed, 56 insertions, 0 deletions

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index c66a9ac7c3d..e35db4387dc 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -20833,6 +20833,62 @@ Perform a vector parallel bit extract operation, as if implemented by
 the Future @code{vpextd} instruction.
 @findex vec_pext
 
+@smallexample
+@exdent vector unsigned char vec_stril (vector unsigned char)
+@exdent vector signed char vec_stril (vector signed char)
+@exdent vector unsigned short vec_stril (vector unsigned short)
+@exdent vector signed short vec_stril (vector signed short)
+@end smallexample
+Isolate the left-most non-zero elements of the incoming vector argument,
+replacing all elements to the right of the left-most zero element
+found within the argument with zero.  The typical implementation uses
+the @code{vstribl} or @code{vstrihl} instruction on big-endian targets
+and uses the @code{vstribr} or @code{vstrihr} instruction on
+little-endian targets.
+@findex vec_stril
+
+@smallexample
+@exdent int vec_stril_p (vector unsigned char)
+@exdent int vec_stril_p (vector signed char)
+@exdent int short vec_stril_p (vector unsigned short)
+@exdent int vec_stril_p (vector signed short)
+@end smallexample
+Return a non-zero value if and only if the argument contains a zero
+element.  The typical implementation uses
+the @code{vstribl.} or @code{vstrihl.} instruction on big-endian targets
+and uses the @code{vstribr.} or @code{vstrihr.} instruction on
+little-endian targets.  Choose this built-in to check for presence of
+zero element if the same argument is also passed to @code{vec_stril}.
+@findex vec_stril_p
+
+@smallexample
+@exdent vector unsigned char vec_strir (vector unsigned char)
+@exdent vector signed char vec_strir (vector signed char)
+@exdent vector unsigned short vec_strir (vector unsigned short)
+@exdent vector signed short vec_strir (vector signed short)
+@end smallexample
+Isolate the right-most non-zero elements of the incoming vector argument,
+replacing all elements to the left of the right-most zero element
+found within the argument with zero.  The typical implementation uses
+the @code{vstribr} or @code{vstrihr} instruction on big-endian targets
+and uses the @code{vstribl} or @code{vstrihl} instruction on
+little-endian targets.
+@findex vec_strir
+
+@smallexample
+@exdent int vec_strir_p (vector unsigned char)
+@exdent int vec_strir_p (vector signed char)
+@exdent int short vec_strir_p (vector unsigned short)
+@exdent int vec_strir_p (vector signed short)
+@end smallexample
+Return a non-zero value if and only if the argument contains a zero
+element.  The typical implementation uses
+the @code{vstribr.} or @code{vstrihr.} instruction on big-endian targets
+and uses the @code{vstribl.} or @code{vstrihl.} instruction on
+little-endian targets.  Choose this built-in to check for presence of
+zero element if the same argument is also passed to @code{vec_strir}.
+@findex vec_strir_p
+
 @node PowerPC Hardware Transactional Memory Built-in Functions
 @subsection PowerPC Hardware Transactional Memory Built-in Functions
 GCC provides two interfaces for accessing the Hardware Transactional