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AgeCommit message (Expand)Author
2015-07-23Fix ubsan signed integer overflowAlan Modra
2015-07-22Fix memory operand size for vcvtt?ps2u?qq instructionsH.J. Lu
2015-07-16Updates the ARM disassembler's output of floating point constants to include ...Alessandro Marzocchi
2015-07-14Sync config/warnings.m4 with GCCH.J. Lu
2015-07-10Add missing changelog entriesAlan Modra
2015-07-03Remove ppc860, ppc750cl, ppc7450 insns from common ppc.Alan Modra
2015-07-01Opcodes and assembler support for Nios II R2Sandra Loosemore
2015-06-30Add support for monitorx/mwaitx instructionsAmit Pawar
2015-06-22PPC sync instruction accepts invalid and incompatible operandsPeter Bergner
2015-06-22Stop "objdump -d" from disassembling past a symbolic address.Nick Clifton
2015-06-19Allow for optional operands with non-zero default values.Peter Bergner
2015-06-16[AArch64] Support id_mmfr4 system registerMatthew Wahab
2015-06-16Fixes a compile time warnng about left shifting a negative value.Szabolcs Nagy
2015-06-12Remove unused MTMSRD_L macro and re-add accidentally deleted comment.Peter Bergner
2015-06-04Add hwsync extended mnemonic.Peter Bergner
2015-06-04Fixes the check for emulated MSP430 instrucrtions that take no operands.Nick Clifton
2015-06-02[ARM] Support for ARMv8.1 Adv.SIMD extensionMatthew Wahab
2015-06-02[ARM] Add support for ARMv8.1 PAN extensionMatthew Wahab
2015-06-02[ARM] Rework CPU feature selection in the disassemblerMatthew Wahab
2015-06-02[AArch64] Support for ARMv8.1a Adv.SIMD instructionsMatthew Wahab
2015-06-02[AArch64] Support for ARMv8.1a Limited Ordering Regions extensionMatthew Wahab
2015-06-01[AArch64][libopcode] Add support for PAN architecture extensionMatthew Wahab
2015-06-01x86/Intel: fix i386_optab[] for vcvt{,u}si2s{d,s}Jan Beulich
2015-06-01x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand orderJan Beulich
2015-06-01x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}Jan Beulich
2015-05-18Remove Disp32 from AMD64 direct call/jmpH.J. Lu
2015-05-15Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu
2015-05-14Fix some PPC assembler errors.Peter Bergner
2015-05-13Add missing ChangeLog entries for PR binutis/18386H.J. Lu
2015-05-11Remove Disp16|Disp32 from 64-bit direct branchesH.J. Lu
2015-05-11Add Intel MCU support to opcodesH.J. Lu
2015-05-09Ignore 0x66 prefix for call/jmp/jcc in 64-bit modeH.J. Lu
2015-04-30Make RL78 disassembler and simulator respect ISA for mul/divDJ Delorie
2015-04-29Updated translations for various binutils components.Nick Clifton
2015-04-27opcodes/Peter Bergner
2015-04-27S/390: Fixes for z13 instructions.Andreas Krebbel
2015-04-23x86: disambiguate disassembly of certain AVX512 insnsJan Beulich
2015-04-15Remove the unused PREFIX_UD_XXXH.J. Lu
2015-04-15Check dp->prefix_requirement insteadH.J. Lu
2015-04-15Handle invalid prefixes for rdrand and rdseedH.J. Lu
2015-04-15Replace mandatory_prefix with prefix_requirementH.J. Lu
2015-04-15[ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2Renlin Li
2015-04-06x86: Use individual prefix control for each opcode.Ilya Tocar
2015-03-30opcodes: d10v: fix old style prototypeMike Frysinger
2015-03-29Add the missing opcodes/ChangeLog entryH.J. Lu
2015-03-29Regenerate opcodes/Makefile.inH.J. Lu
2015-03-26powerpc: Only initialise opcode indices onceAnton Blanchard
2015-03-26powerpc: Add slbfee. instructionAnton Blanchard
2015-03-24Extend arm_feature_set struct to provide more bitsTerry Guo
2015-03-17Add znver1 processorGanesh Gopalasubramanian
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