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AgeCommit message (Expand)Author
2017-11-27Update the simplified Chinese translation of the messages in the opcodes libr...Nick Clifton
2017-11-24x86: don't omit disambiguating suffixes from "fi*"Jan Beulich
2017-11-23Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich
2017-11-23x86: correct UDnJan Beulich
2017-11-22Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor.Igor Tsimbalist
2017-11-22Update ChangeLogIgor Tsimbalist
2017-11-22Remove Vec_Disp8 from vpcompressb and vpexpandb.Igor Tsimbalist
2017-11-22[ARC] Fix handling of ARCv2 H-register class.claziss
2017-11-21[ARC] Improve printing of pc-relative instructions.claziss
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina
2017-11-16Correct AArch64 crypto dependencies.Tamar Christina
2017-11-16Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich
2017-11-15x86: use correct register namesJan Beulich
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich
2017-11-15x86-64: don't allow use of %axl as accumulatorJan Beulich
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich
2017-11-14x86: string insns don't allow displacementsJan Beulich
2017-11-13x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allow q suffixJan Beulich
2017-11-09Add assembler and disassembler support for the new Armv8.4-a registers for AA...Tamar Christina
2017-11-09Add the operand encoding types for the new Armv8.2-a back-ported instructions...Tamar Christina
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options...Tamar Christina
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton
2017-11-08Adds command line support for Armv8.4-A, via the new command line option -mar...Jiong Wang
2017-11-07opcodes/arc: Fix incorrect insn_class for some nps insnsAndrew Burgess
2017-11-07ngettext supportAlan Modra
2017-11-03[ARC] Force the disassam to use the hexadecimal number for printingclaziss
2017-11-03[ARC] Sync opcode data base.claziss
2017-10-25PR22348, conflicting global vars in crx and cr16Alan Modra
2017-10-24RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman
2017-10-23Add missing ChangeLog entriesIgor Tsimbalist
2017-10-23Fix the master due to bad regenerated filesIgor Tsimbalist
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist
2017-10-18[Visium] Disassemble the operands of the stop instruction.Eric Botcazou
2017-10-12FT32: support for FT32B processor - part 1James Bowman
2017-10-09S/390: Sync with latest POP - 3 new instructionsAndreas Krebbel
2017-10-09S/390: Sync with IBM z14 POP - SI_RD formatAndreas Krebbel
2017-10-01Add new mnemonics for VLE multiple load instructionsAlexander Fedotov
2017-09-27Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions,...Nick Clifton
2017-09-26Allow the macw and macl instructions to be used on CPUs that have emacs support.Nick Clifton
2017-09-25Initialize 'imm' on opcodes/aarch64-opc.c:expand_fp_imm (and fix breakage on ...Sergio Durigan Junior
2017-09-11nds32: Rename __BIT() to N32_BIT().Kuan-Lin Chen
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