summaryrefslogtreecommitdiff
path: root/gas/testsuite
AgeCommit message (Expand)Author
2018-01-04RISC-V: Add 2 missing privileged registers.Jim Wilson
2018-01-03Update year range in copyright notice of binutils filesAlan Modra
2017-12-28RISC-V: Add missing privileged spec registers.Jim Wilson
2017-12-20RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson
2017-12-19Correct disassembly of dot product instructions.Tamar Christina
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich
2017-12-17x86: Check pseudo prefix without instructionH.J. Lu
2017-12-14Update the address of the FSF in the copyright notice of files which were usi...Nick Clifton
2017-12-13Add missing RISC-V fsrmi and fsflagsi instructions.Jim Wilson
2017-12-13This patch enables disassembler_needs_relocs for PRU. It is needed to print c...Dimitar Dimitrov
2017-12-04Run powerpc vle gas tests for all powerpc ELF targetsAlan Modra
2017-11-30x86/Intel: issue diagnostics for redundant segment override prefixesJan Beulich
2017-11-30Revert "x86: Update segment register check in Intel syntax"Jan Beulich
2017-11-29Fix riscv malloc error on small alignment after norvc.Jim Wilson
2017-11-29[GAS][AARCH64]Fix a typo for IP1 register alias.Renlin Li
2017-11-27Compress loads/stores with implicit 0 offset.Jim Wilson
2017-11-27gas: xtensa: implement trampoline coalescingMax Filippov
2017-11-27gas: xtensa: reuse trampoline placement codeMax Filippov
2017-11-27gas: xtensa: rewrite xg_relax_trampolineMax Filippov
2017-11-26gas: Update x86 sse-noavx testsH.J. Lu
2017-11-24x86: reject further invalid AVX-512 masking constructsJan Beulich
2017-11-24x86: don't omit disambiguating suffixes from "fi*"Jan Beulich
2017-11-23Fix vax/ns32k/mmix gas testsuite regression.Jim Wilson
2017-11-23Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich
2017-11-23x86-64: always use unsigned 32-bit reloc for 32-bit addressing w/o base regJan Beulich
2017-11-23x86: correct UDnJan Beulich
2017-11-23x86/Intel: don't report multiple errors for a single insn operandJan Beulich
2017-11-22Riscv ld-elf/stab failure and fake label cleanup.Jim Wilson
2017-11-22[ARC] Fix handling of ARCv2 H-register class.claziss
2017-11-21x86: Add tests for -n option of x86 assemblerH.J. Lu
2017-11-21[ARC] Improve printing of pc-relative instructions.claziss
2017-11-21mingw gas testsuite fixAlan Modra
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina
2017-11-16Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich
2017-11-16ix86/Intel: don't require memory operand size specifier for PTWRITEJan Beulich
2017-11-16i386: Replace .code64/.code32 with .byteH.J. Lu
2017-11-15Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a int...Tamar Christina
2017-11-15Add support to readelf and objdump for following links to separate debug info...Nick Clifton
2017-11-15x86: use correct register namesJan Beulich
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich
2017-11-15x86-64: don't allow use of %axl as accumulatorJan Beulich
2017-11-14First part of fix for riscv gas lns-common-1 failure.Jim Wilson
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich
2017-11-14x86: string insns don't allow displacementsJan Beulich
2017-11-13gas/ia64: fix testsuite failuresJan Beulich
2017-11-13x86: don't default variable shift count insns to 8-bit operand sizeJan Beulich