diff options
21 files changed, 244 insertions, 120 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 923f75818f..6fe0983c33 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,26 @@ +2017-11-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com> + + * testsuite/gas/i386/avx512f_vaes-intel.d: Regenerate. + * testsuite/gas/i386/avx512f_vaes.d: Likewise. + * testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Likewise. + * testsuite/gas/i386/avx512f_vaes-wig1.d: Likewise. + * testsuite/gas/i386/avx512vl_vaes-intel.d: Likewise. + * testsuite/gas/i386/avx512vl_vaes.d: Likewise. + * testsuite/gas/i386/x86-64-avx512f_vaes.s: Add instructions with + disp8*N. + * testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Regenerate. + * testsuite/gas/i386/x86-64-avx512f_vaes.d: Likewise. + * testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Add instructions with + disp8*N. + * testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Regenerate. + * testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Likewise. + * testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Regenerate. + * testsuite/gas/i386/x86-64-avx512vl_vaes.d: Likewise. + * testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Add instructions with + disp8*N. + * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Regenerate. + * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Regenerate. + 2017-11-23 Jan Beulich <jbeulich@suse.com> * tc-i386.c (check_VecOperands): Don't clear .disp16. diff --git a/gas/testsuite/gas/i386/avx512f_vaes-intel.d b/gas/testsuite/gas/i386/avx512f_vaes-intel.d index d49cf494d4..e8d0172364 100644 --- a/gas/testsuite/gas/i386/avx512f_vaes-intel.d +++ b/gas/testsuite/gas/i386/avx512f_vaes-intel.d @@ -11,26 +11,26 @@ Disassembly of section \.text: 00000000 <_start>: [ ]*[a-f0-9]+:[ ]*62 f2 55 48 de f4[ ]*vaesdec zmm6,zmm5,zmm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 de b4 f4 c0 1d fe ff[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 48 de b2 c0 1f 00 00[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 de 72 7f[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 48 df f4[ ]*vaesdeclast zmm6,zmm5,zmm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 df b4 f4 c0 1d fe ff[ ]*vaesdeclast zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 48 df b2 c0 1f 00 00[ ]*vaesdeclast zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 df 72 7f[ ]*vaesdeclast zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc f4[ ]*vaesenc zmm6,zmm5,zmm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc b4 f4 c0 1d fe ff[ ]*vaesenc zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc b2 c0 1f 00 00[ ]*vaesenc zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc 72 7f[ ]*vaesenc zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd f4[ ]*vaesenclast zmm6,zmm5,zmm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd b4 f4 c0 1d fe ff[ ]*vaesenclast zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd b2 c0 1f 00 00[ ]*vaesenclast zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd 72 7f[ ]*vaesenclast zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 48 de f4[ ]*vaesdec zmm6,zmm5,zmm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 de b4 f4 c0 1d fe ff[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 48 de b2 c0 1f 00 00[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 de 72 7f[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 48 df f4[ ]*vaesdeclast zmm6,zmm5,zmm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 df b4 f4 c0 1d fe ff[ ]*vaesdeclast zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 48 df b2 c0 1f 00 00[ ]*vaesdeclast zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 df 72 7f[ ]*vaesdeclast zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc f4[ ]*vaesenc zmm6,zmm5,zmm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc b4 f4 c0 1d fe ff[ ]*vaesenc zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc b2 c0 1f 00 00[ ]*vaesenc zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc 72 7f[ ]*vaesenc zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd f4[ ]*vaesenclast zmm6,zmm5,zmm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd b4 f4 c0 1d fe ff[ ]*vaesenclast zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd b2 c0 1f 00 00[ ]*vaesenclast zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd 72 7f[ ]*vaesenclast zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] #pass diff --git a/gas/testsuite/gas/i386/avx512f_vaes-wig1-intel.d b/gas/testsuite/gas/i386/avx512f_vaes-wig1-intel.d index 73562da341..cbc4db14c5 100644 --- a/gas/testsuite/gas/i386/avx512f_vaes-wig1-intel.d +++ b/gas/testsuite/gas/i386/avx512f_vaes-wig1-intel.d @@ -11,26 +11,26 @@ Disassembly of section \.text: 00000000 <_start>: [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de f4[ ]*vaesdec zmm6,zmm5,zmm4 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de b4 f4 c0 1d fe ff[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de b2 c0 1f 00 00[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de 72 7f[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df f4[ ]*vaesdeclast zmm6,zmm5,zmm4 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df b4 f4 c0 1d fe ff[ ]*vaesdeclast zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df b2 c0 1f 00 00[ ]*vaesdeclast zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df 72 7f[ ]*vaesdeclast zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc f4[ ]*vaesenc zmm6,zmm5,zmm4 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc b4 f4 c0 1d fe ff[ ]*vaesenc zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc b2 c0 1f 00 00[ ]*vaesenc zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc 72 7f[ ]*vaesenc zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd f4[ ]*vaesenclast zmm6,zmm5,zmm4 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd b4 f4 c0 1d fe ff[ ]*vaesenclast zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd b2 c0 1f 00 00[ ]*vaesenclast zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd 72 7f[ ]*vaesenclast zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de f4[ ]*vaesdec zmm6,zmm5,zmm4 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de b4 f4 c0 1d fe ff[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de b2 c0 1f 00 00[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de 72 7f[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df f4[ ]*vaesdeclast zmm6,zmm5,zmm4 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df b4 f4 c0 1d fe ff[ ]*vaesdeclast zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df b2 c0 1f 00 00[ ]*vaesdeclast zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df 72 7f[ ]*vaesdeclast zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc f4[ ]*vaesenc zmm6,zmm5,zmm4 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc b4 f4 c0 1d fe ff[ ]*vaesenc zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc b2 c0 1f 00 00[ ]*vaesenc zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc 72 7f[ ]*vaesenc zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd f4[ ]*vaesenclast zmm6,zmm5,zmm4 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd b4 f4 c0 1d fe ff[ ]*vaesenclast zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd b2 c0 1f 00 00[ ]*vaesenclast zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd 72 7f[ ]*vaesenclast zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] #pass diff --git a/gas/testsuite/gas/i386/avx512f_vaes-wig1.d b/gas/testsuite/gas/i386/avx512f_vaes-wig1.d index daa47184e0..f7f2bd9da0 100644 --- a/gas/testsuite/gas/i386/avx512f_vaes-wig1.d +++ b/gas/testsuite/gas/i386/avx512f_vaes-wig1.d @@ -11,26 +11,26 @@ Disassembly of section \.text: 00000000 <_start>: [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de f4[ ]*vaesdec %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de b2 c0 1f 00 00[ ]*vaesdec 0x1fc0\(%edx\),%zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de 72 7f[ ]*vaesdec 0x1fc0\(%edx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df f4[ ]*vaesdeclast %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df b4 f4 c0 1d fe ff[ ]*vaesdeclast -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df b2 c0 1f 00 00[ ]*vaesdeclast 0x1fc0\(%edx\),%zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df 72 7f[ ]*vaesdeclast 0x1fc0\(%edx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc f4[ ]*vaesenc %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc b4 f4 c0 1d fe ff[ ]*vaesenc -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc b2 c0 1f 00 00[ ]*vaesenc 0x1fc0\(%edx\),%zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc 72 7f[ ]*vaesenc 0x1fc0\(%edx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd f4[ ]*vaesenclast %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd b2 c0 1f 00 00[ ]*vaesenclast 0x1fc0\(%edx\),%zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd 72 7f[ ]*vaesenclast 0x1fc0\(%edx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de f4[ ]*vaesdec %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de b2 c0 1f 00 00[ ]*vaesdec 0x1fc0\(%edx\),%zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de 72 7f[ ]*vaesdec 0x1fc0\(%edx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df f4[ ]*vaesdeclast %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df b4 f4 c0 1d fe ff[ ]*vaesdeclast -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df b2 c0 1f 00 00[ ]*vaesdeclast 0x1fc0\(%edx\),%zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df 72 7f[ ]*vaesdeclast 0x1fc0\(%edx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc f4[ ]*vaesenc %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc b4 f4 c0 1d fe ff[ ]*vaesenc -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc b2 c0 1f 00 00[ ]*vaesenc 0x1fc0\(%edx\),%zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc 72 7f[ ]*vaesenc 0x1fc0\(%edx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd f4[ ]*vaesenclast %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd b2 c0 1f 00 00[ ]*vaesenclast 0x1fc0\(%edx\),%zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd 72 7f[ ]*vaesenclast 0x1fc0\(%edx\),%zmm5,%zmm6 #pass diff --git a/gas/testsuite/gas/i386/avx512f_vaes.d b/gas/testsuite/gas/i386/avx512f_vaes.d index 9ba57ac924..50b5ac3dfb 100644 --- a/gas/testsuite/gas/i386/avx512f_vaes.d +++ b/gas/testsuite/gas/i386/avx512f_vaes.d @@ -11,26 +11,26 @@ Disassembly of section \.text: 00000000 <_start>: [ ]*[a-f0-9]+:[ ]*62 f2 55 48 de f4[ ]*vaesdec %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 48 de b2 c0 1f 00 00[ ]*vaesdec 0x1fc0\(%edx\),%zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 de 72 7f[ ]*vaesdec 0x1fc0\(%edx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 df f4[ ]*vaesdeclast %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 df b4 f4 c0 1d fe ff[ ]*vaesdeclast -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 48 df b2 c0 1f 00 00[ ]*vaesdeclast 0x1fc0\(%edx\),%zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 df 72 7f[ ]*vaesdeclast 0x1fc0\(%edx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc f4[ ]*vaesenc %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc b4 f4 c0 1d fe ff[ ]*vaesenc -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc b2 c0 1f 00 00[ ]*vaesenc 0x1fc0\(%edx\),%zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc 72 7f[ ]*vaesenc 0x1fc0\(%edx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd f4[ ]*vaesenclast %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd b2 c0 1f 00 00[ ]*vaesenclast 0x1fc0\(%edx\),%zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd 72 7f[ ]*vaesenclast 0x1fc0\(%edx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 de f4[ ]*vaesdec %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 48 de b2 c0 1f 00 00[ ]*vaesdec 0x1fc0\(%edx\),%zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 de 72 7f[ ]*vaesdec 0x1fc0\(%edx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 df f4[ ]*vaesdeclast %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 df b4 f4 c0 1d fe ff[ ]*vaesdeclast -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 48 df b2 c0 1f 00 00[ ]*vaesdeclast 0x1fc0\(%edx\),%zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 df 72 7f[ ]*vaesdeclast 0x1fc0\(%edx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc f4[ ]*vaesenc %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc b4 f4 c0 1d fe ff[ ]*vaesenc -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc b2 c0 1f 00 00[ ]*vaesenc 0x1fc0\(%edx\),%zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc 72 7f[ ]*vaesenc 0x1fc0\(%edx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd f4[ ]*vaesenclast %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd b2 c0 1f 00 00[ ]*vaesenclast 0x1fc0\(%edx\),%zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd 72 7f[ ]*vaesenclast 0x1fc0\(%edx\),%zmm5,%zmm6 #pass diff --git a/gas/testsuite/gas/i386/avx512vl_vaes-intel.d b/gas/testsuite/gas/i386/avx512vl_vaes-intel.d index 1c235813aa..93f62d002a 100644 --- a/gas/testsuite/gas/i386/avx512vl_vaes-intel.d +++ b/gas/testsuite/gas/i386/avx512vl_vaes-intel.d @@ -35,28 +35,28 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*c4 e2 55 dd b2 e0 0f 00 00[ ]*vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 08 de f4[ ]*vaesdec xmm6,xmm5,xmm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b4 f4 c0 1d fe ff[ ]*vaesdec xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b2 f0 07 00 00[ ]*vaesdec xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de 72 7f[ ]*vaesdec xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 28 de f4[ ]*vaesdec ymm6,ymm5,ymm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b4 f4 c0 1d fe ff[ ]*vaesdec ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b2 e0 0f 00 00[ ]*vaesdec ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de 72 7f[ ]*vaesdec ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 08 df f4[ ]*vaesdeclast xmm6,xmm5,xmm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b4 f4 c0 1d fe ff[ ]*vaesdeclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b2 f0 07 00 00[ ]*vaesdeclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df 72 7f[ ]*vaesdeclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 28 df f4[ ]*vaesdeclast ymm6,ymm5,ymm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b4 f4 c0 1d fe ff[ ]*vaesdeclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b2 e0 0f 00 00[ ]*vaesdeclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df 72 7f[ ]*vaesdeclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc f4[ ]*vaesenc xmm6,xmm5,xmm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ ]*vaesenc xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b2 f0 07 00 00[ ]*vaesenc xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc 72 7f[ ]*vaesenc xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc f4[ ]*vaesenc ymm6,ymm5,ymm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ ]*vaesenc ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b2 e0 0f 00 00[ ]*vaesenc ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc 72 7f[ ]*vaesenc ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd f4[ ]*vaesenclast xmm6,xmm5,xmm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ ]*vaesenclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b2 f0 07 00 00[ ]*vaesenclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd 72 7f[ ]*vaesenclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd f4[ ]*vaesenclast ymm6,ymm5,ymm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ ]*vaesenclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b2 e0 0f 00 00[ ]*vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd 72 7f[ ]*vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*c4 e2 51 de f4[ ]*vaesdec xmm6,xmm5,xmm4 [ ]*[a-f0-9]+:[ ]*c4 e2 51 de b4 f4 c0 1d fe ff[ ]*vaesdec xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\] [ ]*[a-f0-9]+:[ ]*c4 e2 51 de b2 f0 07 00 00[ ]*vaesdec xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] @@ -83,26 +83,26 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*c4 e2 55 dd b2 e0 0f 00 00[ ]*vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 08 de f4[ ]*vaesdec xmm6,xmm5,xmm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b4 f4 c0 1d fe ff[ ]*vaesdec xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b2 f0 07 00 00[ ]*vaesdec xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de 72 7f[ ]*vaesdec xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 28 de f4[ ]*vaesdec ymm6,ymm5,ymm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b4 f4 c0 1d fe ff[ ]*vaesdec ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b2 e0 0f 00 00[ ]*vaesdec ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de 72 7f[ ]*vaesdec ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 08 df f4[ ]*vaesdeclast xmm6,xmm5,xmm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b4 f4 c0 1d fe ff[ ]*vaesdeclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b2 f0 07 00 00[ ]*vaesdeclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df 72 7f[ ]*vaesdeclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 28 df f4[ ]*vaesdeclast ymm6,ymm5,ymm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b4 f4 c0 1d fe ff[ ]*vaesdeclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b2 e0 0f 00 00[ ]*vaesdeclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df 72 7f[ ]*vaesdeclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc f4[ ]*vaesenc xmm6,xmm5,xmm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ ]*vaesenc xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b2 f0 07 00 00[ ]*vaesenc xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc 72 7f[ ]*vaesenc xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc f4[ ]*vaesenc ymm6,ymm5,ymm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ ]*vaesenc ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b2 e0 0f 00 00[ ]*vaesenc ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc 72 7f[ ]*vaesenc ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd f4[ ]*vaesenclast xmm6,xmm5,xmm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ ]*vaesenclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b2 f0 07 00 00[ ]*vaesenclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd 72 7f[ ]*vaesenclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd f4[ ]*vaesenclast ymm6,ymm5,ymm4 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ ]*vaesenclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\] -[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b2 e0 0f 00 00[ ]*vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd 72 7f[ ]*vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\] #pass diff --git a/gas/testsuite/gas/i386/avx512vl_vaes.d b/gas/testsuite/gas/i386/avx512vl_vaes.d index 8d932d5822..ba34ebd014 100644 --- a/gas/testsuite/gas/i386/avx512vl_vaes.d +++ b/gas/testsuite/gas/i386/avx512vl_vaes.d @@ -35,28 +35,28 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*c4 e2 55 dd b2 e0 0f 00 00[ ]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 de f4[ ]*vaesdec %xmm4,%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b2 f0 07 00 00[ ]*vaesdec 0x7f0\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de 72 7f[ ]*vaesdec 0x7f0\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 de f4[ ]*vaesdec %ymm4,%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b2 e0 0f 00 00[ ]*vaesdec 0xfe0\(%edx\),%ymm5,%ymm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de 72 7f[ ]*vaesdec 0xfe0\(%edx\),%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 df f4[ ]*vaesdeclast %xmm4,%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b4 f4 c0 1d fe ff[ ]*vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b2 f0 07 00 00[ ]*vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df 72 7f[ ]*vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 df f4[ ]*vaesdeclast %ymm4,%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b4 f4 c0 1d fe ff[ ]*vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b2 e0 0f 00 00[ ]*vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df 72 7f[ ]*vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc f4[ ]*vaesenc %xmm4,%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ ]*vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b2 f0 07 00 00[ ]*vaesenc 0x7f0\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc 72 7f[ ]*vaesenc 0x7f0\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc f4[ ]*vaesenc %ymm4,%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ ]*vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b2 e0 0f 00 00[ ]*vaesenc 0xfe0\(%edx\),%ymm5,%ymm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc 72 7f[ ]*vaesenc 0xfe0\(%edx\),%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd f4[ ]*vaesenclast %xmm4,%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b2 f0 07 00 00[ ]*vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd 72 7f[ ]*vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd f4[ ]*vaesenclast %ymm4,%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b2 e0 0f 00 00[ ]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd 72 7f[ ]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*c4 e2 51 de f4[ ]*vaesdec %xmm4,%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*c4 e2 51 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*c4 e2 51 de b2 f0 07 00 00[ ]*vaesdec 0x7f0\(%edx\),%xmm5,%xmm6 @@ -83,26 +83,26 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*c4 e2 55 dd b2 e0 0f 00 00[ ]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 de f4[ ]*vaesdec %xmm4,%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b2 f0 07 00 00[ ]*vaesdec 0x7f0\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de 72 7f[ ]*vaesdec 0x7f0\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 de f4[ ]*vaesdec %ymm4,%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b2 e0 0f 00 00[ ]*vaesdec 0xfe0\(%edx\),%ymm5,%ymm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de 72 7f[ ]*vaesdec 0xfe0\(%edx\),%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 df f4[ ]*vaesdeclast %xmm4,%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b4 f4 c0 1d fe ff[ ]*vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b2 f0 07 00 00[ ]*vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df 72 7f[ ]*vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 df f4[ ]*vaesdeclast %ymm4,%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b4 f4 c0 1d fe ff[ ]*vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b2 e0 0f 00 00[ ]*vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df 72 7f[ ]*vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc f4[ ]*vaesenc %xmm4,%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ ]*vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b2 f0 07 00 00[ ]*vaesenc 0x7f0\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc 72 7f[ ]*vaesenc 0x7f0\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc f4[ ]*vaesenc %ymm4,%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ ]*vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b2 e0 0f 00 00[ ]*vaesenc 0xfe0\(%edx\),%ymm5,%ymm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc 72 7f[ ]*vaesenc 0xfe0\(%edx\),%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd f4[ ]*vaesenclast %xmm4,%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b2 f0 07 00 00[ ]*vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd 72 7f[ ]*vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd f4[ ]*vaesenclast %ymm4,%ymm5,%ymm6 [ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6 -[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b2 e0 0f 00 00[ ]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd 72 7f[ ]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6 #pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512f_vaes-intel.d b/gas/testsuite/gas/i386/x86-64-avx512f_vaes-intel.d index 7eacad0d18..f389a5ec22 100644 --- a/gas/testsuite/gas/i386/x86-64-avx512f_vaes-intel.d +++ b/gas/testsuite/gas/i386/x86-64-avx512f_vaes-intel.d @@ -11,18 +11,26 @@ Disassembly of section \.text: 0+ <_start>: [ ]*[a-f0-9]+:[ ]*62 02 15 40 de f4[ ]*vaesdec zmm30,zmm29,zmm28 [ ]*[a-f0-9]+:[ ]*62 22 15 40 de b4 f0 23 01 00 00[ ]*vaesdec zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 de 72 7f[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[rdx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 02 15 40 df f4[ ]*vaesdeclast zmm30,zmm29,zmm28 [ ]*[a-f0-9]+:[ ]*62 22 15 40 df b4 f0 23 01 00 00[ ]*vaesdeclast zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 df 72 7f[ ]*vaesdeclast zmm6,zmm5,ZMMWORD PTR \[rdx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 02 15 40 dc f4[ ]*vaesenc zmm30,zmm29,zmm28 [ ]*[a-f0-9]+:[ ]*62 22 15 40 dc b4 f0 23 01 00 00[ ]*vaesenc zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc 72 7f[ ]*vaesenc zmm6,zmm5,ZMMWORD PTR \[rdx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 02 15 40 dd f4[ ]*vaesenclast zmm30,zmm29,zmm28 [ ]*[a-f0-9]+:[ ]*62 22 15 40 dd b4 f0 23 01 00 00[ ]*vaesenclast zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd 72 7f[ ]*vaesenclast zmm6,zmm5,ZMMWORD PTR \[rdx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 02 15 40 de f4[ ]*vaesdec zmm30,zmm29,zmm28 [ ]*[a-f0-9]+:[ ]*62 22 15 40 de b4 f0 34 12 00 00[ ]*vaesdec zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 de 72 7f[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[rdx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 02 15 40 df f4[ ]*vaesdeclast zmm30,zmm29,zmm28 [ ]*[a-f0-9]+:[ ]*62 22 15 40 df b4 f0 34 12 00 00[ ]*vaesdeclast zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 df 72 7f[ ]*vaesdeclast zmm6,zmm5,ZMMWORD PTR \[rdx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 02 15 40 dc f4[ ]*vaesenc zmm30,zmm29,zmm28 [ ]*[a-f0-9]+:[ ]*62 22 15 40 dc b4 f0 34 12 00 00[ ]*vaesenc zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc 72 7f[ ]*vaesenc zmm6,zmm5,ZMMWORD PTR \[rdx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 02 15 40 dd f4[ ]*vaesenclast zmm30,zmm29,zmm28 [ ]*[a-f0-9]+:[ ]*62 22 15 40 dd b4 f0 34 12 00 00[ ]*vaesenclast zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd 72 7f[ ]*vaesenclast zmm6,zmm5,ZMMWORD PTR \[rdx\+0x1fc0\] #pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512f_vaes-wig.s b/gas/testsuite/gas/i386/x86-64-avx512f_vaes-wig.s index 004a92bf1e..a3f79a32a8 100644 --- a/gas/testsuite/gas/i386/x86-64-avx512f_vaes-wig.s +++ b/gas/testsuite/gas/i386/x86-64-avx512f_vaes-wig.s @@ -5,19 +5,27 @@ _start: vaesdec %zmm28, %zmm29, %zmm30 # AVX512F,VAES vaesdec 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512F,VAES + vaesdec 8128(%rdx), %zmm5, %zmm6 # AVX512F,VAES Disp8 vaesdeclast %zmm28, %zmm29, %zmm30 # AVX512F,VAES vaesdeclast 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512F,VAES + vaesdeclast 8128(%rdx), %zmm5, %zmm6 # AVX512F,VAES Disp8 vaesenc %zmm28, %zmm29, %zmm30 # AVX512F,VAES vaesenc 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512F,VAES + vaesenc 8128(%rdx), %zmm5, %zmm6 # AVX512F,VAES Disp8 vaesenclast %zmm28, %zmm29, %zmm30 # AVX512F,VAES vaesenclast 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512F,VAES + vaesenclast 8128(%rdx), %zmm5, %zmm6 # AVX512F,VAES Disp8 .intel_syntax noprefix vaesdec zmm30, zmm29, zmm28 # AVX512F,VAES vaesdec zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512F,VAES + vaesdec zmm6, zmm5, ZMMWORD PTR [rdx+8128] # AVX512F,VAES Disp8 vaesdeclast zmm30, zmm29, zmm28 # AVX512F,VAES vaesdeclast zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512F,VAES + vaesdeclast zmm6, zmm5, ZMMWORD PTR [rdx+8128] # AVX512F,VAES Disp8 vaesenc zmm30, zmm29, zmm28 # AVX512F,VAES vaesenc zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512F,VAES + vaesenc zmm6, zmm5, ZMMWORD PTR [rdx+8128] # AVX512F,VAES Disp8 vaesenclast zmm30, zmm29, zmm28 # AVX512F,VAES vaesenclast zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512F,VAES + vaesenclast zmm6, zmm5, ZMMWORD PTR [rdx+8128] # AVX512F,VAES Disp8 diff --git a/gas/testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d b/gas/testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d index 171ed57750..a67f8dcaa1 100644 --- a/gas/testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d +++ b/gas/testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d @@ -11,18 +11,26 @@ Disassembly of section \.text: 0+ <_start>: [ ]*[a-f0-9]+:[ ]*62 02 95 40 de f4[ ]*vaesdec zmm30,zmm29,zmm28 [ ]*[a-f0-9]+:[ ]*62 22 95 40 de b4 f0 23 01 00 00[ ]*vaesdec zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de 72 7f[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[rdx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 02 95 40 df f4[ ]*vaesdeclast zmm30,zmm29,zmm28 [ ]*[a-f0-9]+:[ ]*62 22 95 40 df b4 f0 23 01 00 00[ ]*vaesdeclast zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df 72 7f[ ]*vaesdeclast zmm6,zmm5,ZMMWORD PTR \[rdx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 02 95 40 dc f4[ ]*vaesenc zmm30,zmm29,zmm28 [ ]*[a-f0-9]+:[ ]*62 22 95 40 dc b4 f0 23 01 00 00[ ]*vaesenc zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc 72 7f[ ]*vaesenc zmm6,zmm5,ZMMWORD PTR \[rdx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 02 95 40 dd f4[ ]*vaesenclast zmm30,zmm29,zmm28 [ ]*[a-f0-9]+:[ ]*62 22 95 40 dd b4 f0 23 01 00 00[ ]*vaesenclast zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd 72 7f[ ]*vaesenclast zmm6,zmm5,ZMMWORD PTR \[rdx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 02 95 40 de f4[ ]*vaesdec zmm30,zmm29,zmm28 [ ]*[a-f0-9]+:[ ]*62 22 95 40 de b4 f0 34 12 00 00[ ]*vaesdec zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de 72 7f[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[rdx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 02 95 40 df f4[ ]*vaesdeclast zmm30,zmm29,zmm28 [ ]*[a-f0-9]+:[ ]*62 22 95 40 df b4 f0 34 12 00 00[ ]*vaesdeclast zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df 72 7f[ ]*vaesdeclast zmm6,zmm5,ZMMWORD PTR \[rdx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 02 95 40 dc f4[ ]*vaesenc zmm30,zmm29,zmm28 [ ]*[a-f0-9]+:[ ]*62 22 95 40 dc b4 f0 34 12 00 00[ ]*vaesenc zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc 72 7f[ ]*vaesenc zmm6,zmm5,ZMMWORD PTR \[rdx\+0x1fc0\] [ ]*[a-f0-9]+:[ ]*62 02 95 40 dd f4[ ]*vaesenclast zmm30,zmm29,zmm28 [ ]*[a-f0-9]+:[ ]*62 22 95 40 dd b4 f0 34 12 00 00[ ]*vaesenclast zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd 72 7f[ ]*vaesenclast zmm6,zmm5,ZMMWORD PTR \[rdx\+0x1fc0\] #pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d b/gas/testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d index 97b9821e07..a9aa6433b3 100644 --- a/gas/testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d +++ b/gas/testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d @@ -11,18 +11,26 @@ Disassembly of section \.text: 0+ <_start>: [ ]*[a-f0-9]+:[ ]*62 02 95 40 de f4[ ]*vaesdec %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+:[ ]*62 22 95 40 de b4 f0 23 01 00 00[ ]*vaesdec 0x123\(%rax,%r14,8\),%zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de 72 7f[ ]*vaesdec 0x1fc0\(%rdx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 02 95 40 df f4[ ]*vaesdeclast %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+:[ ]*62 22 95 40 df b4 f0 23 01 00 00[ ]*vaesdeclast 0x123\(%rax,%r14,8\),%zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df 72 7f[ ]*vaesdeclast 0x1fc0\(%rdx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 02 95 40 dc f4[ ]*vaesenc %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+:[ ]*62 22 95 40 dc b4 f0 23 01 00 00[ ]*vaesenc 0x123\(%rax,%r14,8\),%zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc 72 7f[ ]*vaesenc 0x1fc0\(%rdx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 02 95 40 dd f4[ ]*vaesenclast %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+:[ ]*62 22 95 40 dd b4 f0 23 01 00 00[ ]*vaesenclast 0x123\(%rax,%r14,8\),%zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd 72 7f[ ]*vaesenclast 0x1fc0\(%rdx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 02 95 40 de f4[ ]*vaesdec %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+:[ ]*62 22 95 40 de b4 f0 34 12 00 00[ ]*vaesdec 0x1234\(%rax,%r14,8\),%zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 de 72 7f[ ]*vaesdec 0x1fc0\(%rdx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 02 95 40 df f4[ ]*vaesdeclast %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+:[ ]*62 22 95 40 df b4 f0 34 12 00 00[ ]*vaesdeclast 0x1234\(%rax,%r14,8\),%zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 df 72 7f[ ]*vaesdeclast 0x1fc0\(%rdx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 02 95 40 dc f4[ ]*vaesenc %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+:[ ]*62 22 95 40 dc b4 f0 34 12 00 00[ ]*vaesenc 0x1234\(%rax,%r14,8\),%zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dc 72 7f[ ]*vaesenc 0x1fc0\(%rdx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 02 95 40 dd f4[ ]*vaesenclast %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+:[ ]*62 22 95 40 dd b4 f0 34 12 00 00[ ]*vaesenclast 0x1234\(%rax,%r14,8\),%zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 dd 72 7f[ ]*vaesenclast 0x1fc0\(%rdx\),%zmm5,%zmm6 #pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512f_vaes.d b/gas/testsuite/gas/i386/x86-64-avx512f_vaes.d index fb66353258..1ebd00528f 100644 --- a/gas/testsuite/gas/i386/x86-64-avx512f_vaes.d +++ b/gas/testsuite/gas/i386/x86-64-avx512f_vaes.d @@ -11,18 +11,26 @@ Disassembly of section \.text: 0+ <_start>: [ ]*[a-f0-9]+:[ ]*62 02 15 40 de f4[ ]*vaesdec %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+:[ ]*62 22 15 40 de b4 f0 23 01 00 00[ ]*vaesdec 0x123\(%rax,%r14,8\),%zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 de 72 7f[ ]*vaesdec 0x1fc0\(%rdx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 02 15 40 df f4[ ]*vaesdeclast %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+:[ ]*62 22 15 40 df b4 f0 23 01 00 00[ ]*vaesdeclast 0x123\(%rax,%r14,8\),%zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 df 72 7f[ ]*vaesdeclast 0x1fc0\(%rdx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 02 15 40 dc f4[ ]*vaesenc %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+:[ ]*62 22 15 40 dc b4 f0 23 01 00 00[ ]*vaesenc 0x123\(%rax,%r14,8\),%zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc 72 7f[ ]*vaesenc 0x1fc0\(%rdx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 02 15 40 dd f4[ ]*vaesenclast %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+:[ ]*62 22 15 40 dd b4 f0 23 01 00 00[ ]*vaesenclast 0x123\(%rax,%r14,8\),%zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd 72 7f[ ]*vaesenclast 0x1fc0\(%rdx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 02 15 40 de f4[ ]*vaesdec %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+:[ ]*62 22 15 40 de b4 f0 34 12 00 00[ ]*vaesdec 0x1234\(%rax,%r14,8\),%zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 de 72 7f[ ]*vaesdec 0x1fc0\(%rdx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 02 15 40 df f4[ ]*vaesdeclast %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+:[ ]*62 22 15 40 df b4 f0 34 12 00 00[ ]*vaesdeclast 0x1234\(%rax,%r14,8\),%zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 df 72 7f[ ]*vaesdeclast 0x1fc0\(%rdx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 02 15 40 dc f4[ ]*vaesenc %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+:[ ]*62 22 15 40 dc b4 f0 34 12 00 00[ ]*vaesenc 0x1234\(%rax,%r14,8\),%zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dc 72 7f[ ]*vaesenc 0x1fc0\(%rdx\),%zmm5,%zmm6 [ ]*[a-f0-9]+:[ ]*62 02 15 40 dd f4[ ]*vaesenclast %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+:[ ]*62 22 15 40 dd b4 f0 34 12 00 00[ ]*vaesenclast 0x1234\(%rax,%r14,8\),%zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 dd 72 7f[ ]*vaesenclast 0x1fc0\(%rdx\),%zmm5,%zmm6 #pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512f_vaes.s b/gas/testsuite/gas/i386/x86-64-avx512f_vaes.s index 6d3eebe8d9..feadd92d8d 100644 --- a/gas/testsuite/gas/i386/x86-64-avx512f_vaes.s +++ b/gas/testsuite/gas/i386/x86-64-avx512f_vaes.s @@ -5,19 +5,27 @@ _start: vaesdec %zmm28, %zmm29, %zmm30 # AVX512F,VAES vaesdec 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512F,VAES + vaesdec 8128(%rdx), %zmm5, %zmm6 # AVX512F,VAES Disp8 vaesdeclast %zmm28, %zmm29, %zmm30 # AVX512F,VAES vaesdeclast 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512F,VAES + vaesdeclast 8128(%rdx), %zmm5, %zmm6 # AVX512F,VAES Disp8 vaesenc %zmm28, %zmm29, %zmm30 # AVX512F,VAES vaesenc 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512F,VAES + vaesenc 8128(%rdx), %zmm5, %zmm6 # AVX512F,VAES Disp8 vaesenclast %zmm28, %zmm29, %zmm30 # AVX512F,VAES vaesenclast 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512F,VAES + vaesenclast 8128(%rdx), %zmm5, %zmm6 # AVX512F,VAES Disp8 .intel_syntax noprefix vaesdec zmm30, zmm29, zmm28 # AVX512F,VAES vaesdec zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512F,VAES + vaesdec zmm6, zmm5, ZMMWORD PTR [rdx+8128] # AVX512F,VAES Disp8 vaesdeclast zmm30, zmm29, zmm28 # AVX512F,VAES vaesdeclast zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512F,VAES + vaesdeclast zmm6, zmm5, ZMMWORD PTR [rdx+8128] # AVX512F,VAES Disp8 vaesenc zmm30, zmm29, zmm28 # AVX512F,VAES vaesenc zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512F,VAES + vaesenc zmm6, zmm5, ZMMWORD PTR [rdx+8128] # AVX512F,VAES Disp8 vaesenclast zmm30, zmm29, zmm28 # AVX512F,VAES vaesenclast zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512F,VAES + vaesenclast zmm6, zmm5, ZMMWORD PTR [rdx+8128] # AVX512F,VAES Disp8 diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d b/gas/testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d index 1c1ad50630..2835374611 100644 --- a/gas/testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d +++ b/gas/testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d @@ -11,51 +11,51 @@ Disassembly of section \.text: 0+ <_start>: [ ]*[a-f0-9]+:[ ]*62 02 15 00 de f4[ ]*vaesdec xmm30,xmm29,xmm28 [ ]*[a-f0-9]+:[ ]*62 22 15 00 de b4 f0 23 01 00 00[ ]*vaesdec xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\] -[ ]*[a-f0-9]+:[ ]*62 62 15 00 de b2 f0 07 00 00[ ]*vaesdec xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 62 15 00 de 72 7f[ ]*vaesdec xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 02 15 20 de f4[ ]*vaesdec ymm30,ymm29,ymm28 [ ]*[a-f0-9]+:[ ]*62 62 15 20 de 31[ ]*vaesdec ymm30,ymm29,YMMWORD PTR \[rcx\] [ ]*[a-f0-9]+:[ ]*62 22 15 20 de b4 f0 23 01 00 00[ ]*vaesdec ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\] -[ ]*[a-f0-9]+:[ ]*62 62 15 20 de b2 e0 0f 00 00[ ]*vaesdec ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 62 15 20 de 72 7f[ ]*vaesdec ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 02 15 00 df f4[ ]*vaesdeclast xmm30,xmm29,xmm28 [ ]*[a-f0-9]+:[ ]*62 22 15 00 df b4 f0 23 01 00 00[ ]*vaesdeclast xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\] -[ ]*[a-f0-9]+:[ ]*62 62 15 00 df b2 f0 07 00 00[ ]*vaesdeclast xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 62 15 00 df 72 7f[ ]*vaesdeclast xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 02 15 20 df f4[ ]*vaesdeclast ymm30,ymm29,ymm28 [ ]*[a-f0-9]+:[ ]*62 22 15 20 df b4 f0 23 01 00 00[ ]*vaesdeclast ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\] -[ ]*[a-f0-9]+:[ ]*62 62 15 20 df b2 e0 0f 00 00[ ]*vaesdeclast ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 62 15 20 df 72 7f[ ]*vaesdeclast ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 02 15 00 dc f4[ ]*vaesenc xmm30,xmm29,xmm28 [ ]*[a-f0-9]+:[ ]*62 22 15 00 dc b4 f0 23 01 00 00[ ]*vaesenc xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\] -[ ]*[a-f0-9]+:[ ]*62 62 15 00 dc b2 f0 07 00 00[ ]*vaesenc xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 62 15 00 dc 72 7f[ ]*vaesenc xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 02 15 20 dc f4[ ]*vaesenc ymm30,ymm29,ymm28 [ ]*[a-f0-9]+:[ ]*62 22 15 20 dc b4 f0 23 01 00 00[ ]*vaesenc ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\] -[ ]*[a-f0-9]+:[ ]*62 62 15 20 dc b2 e0 0f 00 00[ ]*vaesenc ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 62 15 20 dc 72 7f[ ]*vaesenc ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 02 15 00 dd f4[ ]*vaesenclast xmm30,xmm29,xmm28 [ ]*[a-f0-9]+:[ ]*62 22 15 00 dd b4 f0 23 01 00 00[ ]*vaesenclast xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\] -[ ]*[a-f0-9]+:[ ]*62 62 15 00 dd b2 f0 07 00 00[ ]*vaesenclast xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 62 15 00 dd 72 7f[ ]*vaesenclast xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 02 15 20 dd f4[ ]*vaesenclast ymm30,ymm29,ymm28 [ ]*[a-f0-9]+:[ ]*62 22 15 20 dd b4 f0 23 01 00 00[ ]*vaesenclast ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\] -[ ]*[a-f0-9]+:[ ]*62 62 15 20 dd b2 e0 0f 00 00[ ]*vaesenclast ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 62 15 20 dd 72 7f[ ]*vaesenclast ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 02 15 00 de f4[ ]*vaesdec xmm30,xmm29,xmm28 [ ]*[a-f0-9]+:[ ]*62 22 15 00 de b4 f0 34 12 00 00[ ]*vaesdec xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\] -[ ]*[a-f0-9]+:[ ]*62 62 15 00 de b2 f0 07 00 00[ ]*vaesdec xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 62 15 00 de 72 7f[ ]*vaesdec xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 02 15 20 de f4[ ]*vaesdec ymm30,ymm29,ymm28 [ ]*[a-f0-9]+:[ ]*62 22 15 20 de b4 f0 34 12 00 00[ ]*vaesdec ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\] -[ ]*[a-f0-9]+:[ ]*62 62 15 20 de b2 e0 0f 00 00[ ]*vaesdec ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 62 15 20 de 72 7f[ ]*vaesdec ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 02 15 00 df f4[ ]*vaesdeclast xmm30,xmm29,xmm28 [ ]*[a-f0-9]+:[ ]*62 22 15 00 df b4 f0 34 12 00 00[ ]*vaesdeclast xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\] -[ ]*[a-f0-9]+:[ ]*62 62 15 00 df b2 f0 07 00 00[ ]*vaesdeclast xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 62 15 00 df 72 7f[ ]*vaesdeclast xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 02 15 20 df f4[ ]*vaesdeclast ymm30,ymm29,ymm28 [ ]*[a-f0-9]+:[ ]*62 22 15 20 df b4 f0 34 12 00 00[ ]*vaesdeclast ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\] -[ ]*[a-f0-9]+:[ ]*62 62 15 20 df b2 e0 0f 00 00[ ]*vaesdeclast ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 62 15 20 df 72 7f[ ]*vaesdeclast ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 02 15 00 dc f4[ ]*vaesenc xmm30,xmm29,xmm28 [ ]*[a-f0-9]+:[ ]*62 22 15 00 dc b4 f0 34 12 00 00[ ]*vaesenc xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\] -[ ]*[a-f0-9]+:[ ]*62 62 15 00 dc b2 f0 07 00 00[ ]*vaesenc xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 62 15 00 dc 72 7f[ ]*vaesenc xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 02 15 20 dc f4[ ]*vaesenc ymm30,ymm29,ymm28 [ ]*[a-f0-9]+:[ ]*62 22 15 20 dc b4 f0 34 12 00 00[ ]*vaesenc ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\] -[ ]*[a-f0-9]+:[ ]*62 62 15 20 dc b2 e0 0f 00 00[ ]*vaesenc ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 62 15 20 dc 72 7f[ ]*vaesenc ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 02 15 00 dd f4[ ]*vaesenclast xmm30,xmm29,xmm28 [ ]*[a-f0-9]+:[ ]*62 22 15 00 dd b4 f0 34 12 00 00[ ]*vaesenclast xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\] -[ ]*[a-f0-9]+:[ ]*62 62 15 00 dd b2 f0 07 00 00[ ]*vaesenclast xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 62 15 00 dd 72 7f[ ]*vaesenclast xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 02 15 20 dd f4[ ]*vaesenclast ymm30,ymm29,ymm28 [ ]*[a-f0-9]+:[ ]*62 22 15 20 dd b4 f0 34 12 00 00[ ]*vaesenclast ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\] -[ ]*[a-f0-9]+:[ ]*62 62 15 20 dd b2 e0 0f 00 00[ ]*vaesenclast ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 62 15 20 dd 72 7f[ ]*vaesenclast ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] #pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s b/gas/testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s index e287c486fa..9dff0bc374 100644 --- a/gas/testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s +++ b/gas/testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s @@ -5,35 +5,51 @@ _start: vaesdec %xmm28, %xmm29, %xmm30 # AVX512VL,VAES vaesdec 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512VL,VAES + vaesdec 2032(%rdx), %xmm29, %xmm30 # AVX512VL,VAES Disp8 vaesdec %ymm28, %ymm29, %ymm30 # AVX512VL,VAES vaesdec 0x123(%rax,%r14,8), %ymm29, %ymm30 # AVX512VL,VAES + vaesdec 4064(%rdx), %ymm29, %ymm30 # AVX512VL,VAES Disp8 vaesdeclast %xmm28, %xmm29, %xmm30 # AVX512VL,VAES vaesdeclast 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512VL,VAES + vaesdeclast 2032(%rdx), %xmm29, %xmm30 # AVX512VL,VAES Disp8 vaesdeclast %ymm28, %ymm29, %ymm30 # AVX512VL,VAES vaesdeclast 0x123(%rax,%r14,8), %ymm29, %ymm30 # AVX512VL,VAES + vaesdeclast 4064(%rdx), %ymm29, %ymm30 # AVX512VL,VAES Disp8 vaesenc %xmm28, %xmm29, %xmm30 # AVX512VL,VAES vaesenc 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512VL,VAES + vaesenc 2032(%rdx), %xmm29, %xmm30 # AVX512VL,VAES Disp8 vaesenc %ymm28, %ymm29, %ymm30 # AVX512VL,VAES vaesenc 0x123(%rax,%r14,8), %ymm29, %ymm30 # AVX512VL,VAES + vaesenc 4064(%rdx), %ymm29, %ymm30 # AVX512VL,VAES Disp8 vaesenclast %xmm28, %xmm29, %xmm30 # AVX512VL,VAES vaesenclast 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512VL,VAES + vaesenclast 2032(%rdx), %xmm29, %xmm30 # AVX512VL,VAES Disp8 vaesenclast %ymm28, %ymm29, %ymm30 # AVX512VL,VAES vaesenclast 0x123(%rax,%r14,8), %ymm29, %ymm30 # AVX512VL,VAES + vaesenclast 4064(%rdx), %ymm29, %ymm30 # AVX512VL,VAES Disp8 .intel_syntax noprefix vaesdec xmm30, xmm29, xmm28 # AVX512VL,VAES vaesdec xmm30, xmm29, XMMWORD PTR [rax+r14*8+0x1234] # AVX512VL,VAES + vaesdec xmm30, xmm29, XMMWORD PTR [rdx+2032] # AVX512VL,VAES Disp8 vaesdec ymm30, ymm29, ymm28 # AVX512VL,VAES vaesdec ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234] # AVX512VL,VAES + vaesdec ymm30, ymm29, YMMWORD PTR [rdx+4064] # AVX512VL,VAES Disp8 vaesdeclast xmm30, xmm29, xmm28 # AVX512VL,VAES vaesdeclast xmm30, xmm29, XMMWORD PTR [rax+r14*8+0x1234] # AVX512VL,VAES + vaesdeclast xmm30, xmm29, XMMWORD PTR [rdx+2032] # AVX512VL,VAES Disp8 vaesdeclast ymm30, ymm29, ymm28 # AVX512VL,VAES vaesdeclast ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234] # AVX512VL,VAES + vaesdeclast ymm30, ymm29, YMMWORD PTR [rdx+4064] # AVX512VL,VAES Disp8 vaesenc xmm30, xmm29, xmm28 # AVX512VL,VAES vaesenc xmm30, xmm29, XMMWORD PTR [rax+r14*8+0x1234] # AVX512VL,VAES + vaesenc xmm30, xmm29, XMMWORD PTR [rdx+2032] # AVX512VL,VAES Disp8 vaesenc ymm30, ymm29, ymm28 # AVX512VL,VAES vaesenc ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234] # AVX512VL,VAES + vaesenc ymm30, ymm29, YMMWORD PTR [rdx+4064] # AVX512VL,VAES Disp8 vaesenclast xmm30, xmm29, xmm28 # AVX512VL,VAES vaesenclast xmm30, xmm29, XMMWORD PTR [rax+r14*8+0x1234] # AVX512VL,VAES + vaesenclast xmm30, xmm29, XMMWORD PTR [rdx+2032] # AVX512VL,VAES Disp8 vaesenclast ymm30, ymm29, ymm28 # AVX512VL,VAES vaesenclast ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234] # AVX512VL,VAES + vaesenclast ymm30, ymm29, YMMWORD PTR [rdx+4064] # AVX512VL,VAES Disp8 diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d b/gas/testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d index ccd8607d55..35f7489ae2 100644 --- a/gas/testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d +++ b/gas/testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d @@ -11,34 +11,50 @@ Disassembly of section \.text: 0+ <_start>: [ ]*[a-f0-9]+:[ ]*62 02 95 00 de f4[ ]*vaesdec xmm30,xmm29,xmm28 [ ]*[a-f0-9]+:[ ]*62 22 95 00 de b4 f0 23 01 00 00[ ]*vaesdec xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 95 00 de 72 7f[ ]*vaesdec xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 02 95 20 de f4[ ]*vaesdec ymm30,ymm29,ymm28 [ ]*[a-f0-9]+:[ ]*62 22 95 20 de b4 f0 23 01 00 00[ ]*vaesdec ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 95 20 de 72 7f[ ]*vaesdec ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 02 95 00 df f4[ ]*vaesdeclast xmm30,xmm29,xmm28 [ ]*[a-f0-9]+:[ ]*62 22 95 00 df b4 f0 23 01 00 00[ ]*vaesdeclast xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 95 00 df 72 7f[ ]*vaesdeclast xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 02 95 20 df f4[ ]*vaesdeclast ymm30,ymm29,ymm28 [ ]*[a-f0-9]+:[ ]*62 22 95 20 df b4 f0 23 01 00 00[ ]*vaesdeclast ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 95 20 df 72 7f[ ]*vaesdeclast ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 02 95 00 dc f4[ ]*vaesenc xmm30,xmm29,xmm28 [ ]*[a-f0-9]+:[ ]*62 22 95 00 dc b4 f0 23 01 00 00[ ]*vaesenc xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 95 00 dc 72 7f[ ]*vaesenc xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 02 95 20 dc f4[ ]*vaesenc ymm30,ymm29,ymm28 [ ]*[a-f0-9]+:[ ]*62 22 95 20 dc b4 f0 23 01 00 00[ ]*vaesenc ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 95 20 dc 72 7f[ ]*vaesenc ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 02 95 00 dd f4[ ]*vaesenclast xmm30,xmm29,xmm28 [ ]*[a-f0-9]+:[ ]*62 22 95 00 dd b4 f0 23 01 00 00[ ]*vaesenclast xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 95 00 dd 72 7f[ ]*vaesenclast xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 02 95 20 dd f4[ ]*vaesenclast ymm30,ymm29,ymm28 [ ]*[a-f0-9]+:[ ]*62 22 95 20 dd b4 f0 23 01 00 00[ ]*vaesenclast ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 95 20 dd 72 7f[ ]*vaesenclast ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 02 95 00 de f4[ ]*vaesdec xmm30,xmm29,xmm28 [ ]*[a-f0-9]+:[ ]*62 22 95 00 de b4 f0 34 12 00 00[ ]*vaesdec xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 95 00 de 72 7f[ ]*vaesdec xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 02 95 20 de f4[ ]*vaesdec ymm30,ymm29,ymm28 [ ]*[a-f0-9]+:[ ]*62 22 95 20 de b4 f0 34 12 00 00[ ]*vaesdec ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 95 20 de 72 7f[ ]*vaesdec ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 02 95 00 df f4[ ]*vaesdeclast xmm30,xmm29,xmm28 [ ]*[a-f0-9]+:[ ]*62 22 95 00 df b4 f0 34 12 00 00[ ]*vaesdeclast xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 95 00 df 72 7f[ ]*vaesdeclast xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 02 95 20 df f4[ ]*vaesdeclast ymm30,ymm29,ymm28 [ ]*[a-f0-9]+:[ ]*62 22 95 20 df b4 f0 34 12 00 00[ ]*vaesdeclast ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 95 20 df 72 7f[ ]*vaesdeclast ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 02 95 00 dc f4[ ]*vaesenc xmm30,xmm29,xmm28 [ ]*[a-f0-9]+:[ ]*62 22 95 00 dc b4 f0 34 12 00 00[ ]*vaesenc xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 95 00 dc 72 7f[ ]*vaesenc xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 02 95 20 dc f4[ ]*vaesenc ymm30,ymm29,ymm28 [ ]*[a-f0-9]+:[ ]*62 22 95 20 dc b4 f0 34 12 00 00[ ]*vaesenc ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 95 20 dc 72 7f[ ]*vaesenc ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] [ ]*[a-f0-9]+:[ ]*62 02 95 00 dd f4[ ]*vaesenclast xmm30,xmm29,xmm28 [ ]*[a-f0-9]+:[ ]*62 22 95 00 dd b4 f0 34 12 00 00[ ]*vaesenclast xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 95 00 dd 72 7f[ ]*vaesenclast xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\] [ ]*[a-f0-9]+:[ ]*62 02 95 20 dd f4[ ]*vaesenclast ymm30,ymm29,ymm28 [ ]*[a-f0-9]+:[ ]*62 22 95 20 dd b4 f0 34 12 00 00[ ]*vaesenclast ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 95 20 dd 72 7f[ ]*vaesenclast ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\] #pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d b/gas/testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d index 1fb280b3e1..5b3f527739 100644 --- a/gas/testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d +++ b/gas/testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d @@ -11,34 +11,50 @@ Disassembly of section \.text: 0+ <_start>: [ ]*[a-f0-9]+:[ ]*62 02 95 00 de f4[ ]*vaesdec %xmm28,%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 22 95 00 de b4 f0 23 01 00 00[ ]*vaesdec 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 95 00 de 72 7f[ ]*vaesdec 0x7f0\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 02 95 20 de f4[ ]*vaesdec %ymm28,%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 22 95 20 de b4 f0 23 01 00 00[ ]*vaesdec 0x123\(%rax,%r14,8\),%ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 95 20 de 72 7f[ ]*vaesdec 0xfe0\(%rdx\),%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 02 95 00 df f4[ ]*vaesdeclast %xmm28,%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 22 95 00 df b4 f0 23 01 00 00[ ]*vaesdeclast 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 95 00 df 72 7f[ ]*vaesdeclast 0x7f0\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 02 95 20 df f4[ ]*vaesdeclast %ymm28,%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 22 95 20 df b4 f0 23 01 00 00[ ]*vaesdeclast 0x123\(%rax,%r14,8\),%ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 95 20 df 72 7f[ ]*vaesdeclast 0xfe0\(%rdx\),%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 02 95 00 dc f4[ ]*vaesenc %xmm28,%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 22 95 00 dc b4 f0 23 01 00 00[ ]*vaesenc 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 95 00 dc 72 7f[ ]*vaesenc 0x7f0\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 02 95 20 dc f4[ ]*vaesenc %ymm28,%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 22 95 20 dc b4 f0 23 01 00 00[ ]*vaesenc 0x123\(%rax,%r14,8\),%ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 95 20 dc 72 7f[ ]*vaesenc 0xfe0\(%rdx\),%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 02 95 00 dd f4[ ]*vaesenclast %xmm28,%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 22 95 00 dd b4 f0 23 01 00 00[ ]*vaesenclast 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 95 00 dd 72 7f[ ]*vaesenclast 0x7f0\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 02 95 20 dd f4[ ]*vaesenclast %ymm28,%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 22 95 20 dd b4 f0 23 01 00 00[ ]*vaesenclast 0x123\(%rax,%r14,8\),%ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 95 20 dd 72 7f[ ]*vaesenclast 0xfe0\(%rdx\),%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 02 95 00 de f4[ ]*vaesdec %xmm28,%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 22 95 00 de b4 f0 34 12 00 00[ ]*vaesdec 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 95 00 de 72 7f[ ]*vaesdec 0x7f0\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 02 95 20 de f4[ ]*vaesdec %ymm28,%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 22 95 20 de b4 f0 34 12 00 00[ ]*vaesdec 0x1234\(%rax,%r14,8\),%ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 95 20 de 72 7f[ ]*vaesdec 0xfe0\(%rdx\),%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 02 95 00 df f4[ ]*vaesdeclast %xmm28,%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 22 95 00 df b4 f0 34 12 00 00[ ]*vaesdeclast 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 95 00 df 72 7f[ ]*vaesdeclast 0x7f0\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 02 95 20 df f4[ ]*vaesdeclast %ymm28,%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 22 95 20 df b4 f0 34 12 00 00[ ]*vaesdeclast 0x1234\(%rax,%r14,8\),%ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 95 20 df 72 7f[ ]*vaesdeclast 0xfe0\(%rdx\),%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 02 95 00 dc f4[ ]*vaesenc %xmm28,%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 22 95 00 dc b4 f0 34 12 00 00[ ]*vaesenc 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 95 00 dc 72 7f[ ]*vaesenc 0x7f0\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 02 95 20 dc f4[ ]*vaesenc %ymm28,%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 22 95 20 dc b4 f0 34 12 00 00[ ]*vaesenc 0x1234\(%rax,%r14,8\),%ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 95 20 dc 72 7f[ ]*vaesenc 0xfe0\(%rdx\),%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 02 95 00 dd f4[ ]*vaesenclast %xmm28,%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 22 95 00 dd b4 f0 34 12 00 00[ ]*vaesenclast 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 95 00 dd 72 7f[ ]*vaesenclast 0x7f0\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 02 95 20 dd f4[ ]*vaesenclast %ymm28,%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 22 95 20 dd b4 f0 34 12 00 00[ ]*vaesenclast 0x1234\(%rax,%r14,8\),%ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 95 20 dd 72 7f[ ]*vaesenclast 0xfe0\(%rdx\),%ymm29,%ymm30 #pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl_vaes.d b/gas/testsuite/gas/i386/x86-64-avx512vl_vaes.d index fb87e8d408..2c03e57904 100644 --- a/gas/testsuite/gas/i386/x86-64-avx512vl_vaes.d +++ b/gas/testsuite/gas/i386/x86-64-avx512vl_vaes.d @@ -11,51 +11,51 @@ Disassembly of section \.text: 0+ <_start>: [ ]*[a-f0-9]+:[ ]*62 02 15 00 de f4[ ]*vaesdec %xmm28,%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 22 15 00 de b4 f0 23 01 00 00[ ]*vaesdec 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+:[ ]*62 62 15 00 de b2 f0 07 00 00[ ]*vaesdec 0x7f0\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 15 00 de 72 7f[ ]*vaesdec 0x7f0\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 02 15 20 de f4[ ]*vaesdec %ymm28,%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 62 15 20 de 31[ ]*vaesdec \(%rcx\),%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 22 15 20 de b4 f0 23 01 00 00[ ]*vaesdec 0x123\(%rax,%r14,8\),%ymm29,%ymm30 -[ ]*[a-f0-9]+:[ ]*62 62 15 20 de b2 e0 0f 00 00[ ]*vaesdec 0xfe0\(%rdx\),%ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 15 20 de 72 7f[ ]*vaesdec 0xfe0\(%rdx\),%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 02 15 00 df f4[ ]*vaesdeclast %xmm28,%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 22 15 00 df b4 f0 23 01 00 00[ ]*vaesdeclast 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+:[ ]*62 62 15 00 df b2 f0 07 00 00[ ]*vaesdeclast 0x7f0\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 15 00 df 72 7f[ ]*vaesdeclast 0x7f0\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 02 15 20 df f4[ ]*vaesdeclast %ymm28,%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 22 15 20 df b4 f0 23 01 00 00[ ]*vaesdeclast 0x123\(%rax,%r14,8\),%ymm29,%ymm30 -[ ]*[a-f0-9]+:[ ]*62 62 15 20 df b2 e0 0f 00 00[ ]*vaesdeclast 0xfe0\(%rdx\),%ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 15 20 df 72 7f[ ]*vaesdeclast 0xfe0\(%rdx\),%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 02 15 00 dc f4[ ]*vaesenc %xmm28,%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 22 15 00 dc b4 f0 23 01 00 00[ ]*vaesenc 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+:[ ]*62 62 15 00 dc b2 f0 07 00 00[ ]*vaesenc 0x7f0\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 15 00 dc 72 7f[ ]*vaesenc 0x7f0\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 02 15 20 dc f4[ ]*vaesenc %ymm28,%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 22 15 20 dc b4 f0 23 01 00 00[ ]*vaesenc 0x123\(%rax,%r14,8\),%ymm29,%ymm30 -[ ]*[a-f0-9]+:[ ]*62 62 15 20 dc b2 e0 0f 00 00[ ]*vaesenc 0xfe0\(%rdx\),%ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 15 20 dc 72 7f[ ]*vaesenc 0xfe0\(%rdx\),%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 02 15 00 dd f4[ ]*vaesenclast %xmm28,%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 22 15 00 dd b4 f0 23 01 00 00[ ]*vaesenclast 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+:[ ]*62 62 15 00 dd b2 f0 07 00 00[ ]*vaesenclast 0x7f0\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 15 00 dd 72 7f[ ]*vaesenclast 0x7f0\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 02 15 20 dd f4[ ]*vaesenclast %ymm28,%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 22 15 20 dd b4 f0 23 01 00 00[ ]*vaesenclast 0x123\(%rax,%r14,8\),%ymm29,%ymm30 -[ ]*[a-f0-9]+:[ ]*62 62 15 20 dd b2 e0 0f 00 00[ ]*vaesenclast 0xfe0\(%rdx\),%ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 15 20 dd 72 7f[ ]*vaesenclast 0xfe0\(%rdx\),%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 02 15 00 de f4[ ]*vaesdec %xmm28,%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 22 15 00 de b4 f0 34 12 00 00[ ]*vaesdec 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+:[ ]*62 62 15 00 de b2 f0 07 00 00[ ]*vaesdec 0x7f0\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 15 00 de 72 7f[ ]*vaesdec 0x7f0\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 02 15 20 de f4[ ]*vaesdec %ymm28,%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 22 15 20 de b4 f0 34 12 00 00[ ]*vaesdec 0x1234\(%rax,%r14,8\),%ymm29,%ymm30 -[ ]*[a-f0-9]+:[ ]*62 62 15 20 de b2 e0 0f 00 00[ ]*vaesdec 0xfe0\(%rdx\),%ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 15 20 de 72 7f[ ]*vaesdec 0xfe0\(%rdx\),%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 02 15 00 df f4[ ]*vaesdeclast %xmm28,%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 22 15 00 df b4 f0 34 12 00 00[ ]*vaesdeclast 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+:[ ]*62 62 15 00 df b2 f0 07 00 00[ ]*vaesdeclast 0x7f0\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 15 00 df 72 7f[ ]*vaesdeclast 0x7f0\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 02 15 20 df f4[ ]*vaesdeclast %ymm28,%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 22 15 20 df b4 f0 34 12 00 00[ ]*vaesdeclast 0x1234\(%rax,%r14,8\),%ymm29,%ymm30 -[ ]*[a-f0-9]+:[ ]*62 62 15 20 df b2 e0 0f 00 00[ ]*vaesdeclast 0xfe0\(%rdx\),%ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 15 20 df 72 7f[ ]*vaesdeclast 0xfe0\(%rdx\),%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 02 15 00 dc f4[ ]*vaesenc %xmm28,%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 22 15 00 dc b4 f0 34 12 00 00[ ]*vaesenc 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+:[ ]*62 62 15 00 dc b2 f0 07 00 00[ ]*vaesenc 0x7f0\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 15 00 dc 72 7f[ ]*vaesenc 0x7f0\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 02 15 20 dc f4[ ]*vaesenc %ymm28,%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 22 15 20 dc b4 f0 34 12 00 00[ ]*vaesenc 0x1234\(%rax,%r14,8\),%ymm29,%ymm30 -[ ]*[a-f0-9]+:[ ]*62 62 15 20 dc b2 e0 0f 00 00[ ]*vaesenc 0xfe0\(%rdx\),%ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 15 20 dc 72 7f[ ]*vaesenc 0xfe0\(%rdx\),%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 02 15 00 dd f4[ ]*vaesenclast %xmm28,%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 22 15 00 dd b4 f0 34 12 00 00[ ]*vaesenclast 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+:[ ]*62 62 15 00 dd b2 f0 07 00 00[ ]*vaesenclast 0x7f0\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 15 00 dd 72 7f[ ]*vaesenclast 0x7f0\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+:[ ]*62 02 15 20 dd f4[ ]*vaesenclast %ymm28,%ymm29,%ymm30 [ ]*[a-f0-9]+:[ ]*62 22 15 20 dd b4 f0 34 12 00 00[ ]*vaesenclast 0x1234\(%rax,%r14,8\),%ymm29,%ymm30 -[ ]*[a-f0-9]+:[ ]*62 62 15 20 dd b2 e0 0f 00 00[ ]*vaesenclast 0xfe0\(%rdx\),%ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 15 20 dd 72 7f[ ]*vaesenclast 0xfe0\(%rdx\),%ymm29,%ymm30 #pass diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index c1a1e5ef67..fdae24cfaa 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2017-11-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com> + + * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions. + * i386-tbl.h: Regenerate. + 2017-11-23 Jan Beulich <jbeulich@suse.com> * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index eb4d62f008..add5ac9c81 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -6206,18 +6206,18 @@ vgf2p8mulb, 3, 0x66cf, None, 1, CpuGFNI|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexO // AVX512 + VAES instructions -vaesdec, 3, 0x66de, None, 1, CpuAVX512F|CpuVAES, Modrm|EVex=1|VexOpcode=1|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM } -vaesdec, 3, 0x66de, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=2|VexOpcode=1|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } -vaesdec, 3, 0x66de, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=3|VexOpcode=1|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM } -vaesdeclast, 3, 0x66df, None, 1, CpuAVX512F|CpuVAES, Modrm|EVex=1|VexOpcode=1|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM } -vaesdeclast, 3, 0x66df, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=2|VexOpcode=1|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } -vaesdeclast, 3, 0x66df, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=3|VexOpcode=1|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM } -vaesenc, 3, 0x66dc, None, 1, CpuAVX512F|CpuVAES, Modrm|EVex=1|VexOpcode=1|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM } -vaesenc, 3, 0x66dc, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=2|VexOpcode=1|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } -vaesenc, 3, 0x66dc, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=3|VexOpcode=1|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM } -vaesenclast, 3, 0x66dd, None, 1, CpuAVX512F|CpuVAES, Modrm|EVex=1|VexOpcode=1|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM } -vaesenclast, 3, 0x66dd, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=2|VexOpcode=1|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } -vaesenclast, 3, 0x66dd, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=3|VexOpcode=1|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM } +vaesdec, 3, 0x66de, None, 1, CpuAVX512F|CpuVAES, Modrm|EVex=1|VexOpcode=1|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM } +vaesdec, 3, 0x66de, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=2|VexOpcode=1|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } +vaesdec, 3, 0x66de, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM } +vaesdeclast, 3, 0x66df, None, 1, CpuAVX512F|CpuVAES, Modrm|EVex=1|VexOpcode=1|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM } +vaesdeclast, 3, 0x66df, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=2|VexOpcode=1|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } +vaesdeclast, 3, 0x66df, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM } +vaesenc, 3, 0x66dc, None, 1, CpuAVX512F|CpuVAES, Modrm|EVex=1|VexOpcode=1|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM } +vaesenc, 3, 0x66dc, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=2|VexOpcode=1|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } +vaesenc, 3, 0x66dc, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM } +vaesenclast, 3, 0x66dd, None, 1, CpuAVX512F|CpuVAES, Modrm|EVex=1|VexOpcode=1|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM } +vaesenclast, 3, 0x66dd, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=2|VexOpcode=1|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } +vaesenclast, 3, 0x66dd, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM } // AVX512 + VAES instructions end diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 33a885088b..32622c2830 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -24237,7 +24237,7 @@ const insn_template i386_optab[] = 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -24257,7 +24257,7 @@ const insn_template i386_optab[] = 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -24277,7 +24277,7 @@ const insn_template i386_optab[] = 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -24337,7 +24337,7 @@ const insn_template i386_optab[] = 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -24357,7 +24357,7 @@ const insn_template i386_optab[] = 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -24377,7 +24377,7 @@ const insn_template i386_optab[] = 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -24437,7 +24437,7 @@ const insn_template i386_optab[] = 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -24457,7 +24457,7 @@ const insn_template i386_optab[] = 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -24477,7 +24477,7 @@ const insn_template i386_optab[] = 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -24537,7 +24537,7 @@ const insn_template i386_optab[] = 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -24557,7 +24557,7 @@ const insn_template i386_optab[] = 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -24577,7 +24577,7 @@ const insn_template i386_optab[] = 0, 0, 0 } }, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |