diff options
| author | Tamar Christina <tamar.christina@arm.com> | 2017-12-19 12:05:20 +0000 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2017-12-19 12:21:12 +0000 |
| commit | 00c2093f698e8f40c04340cb1832d09e11ece237 (patch) | |
| tree | ff7998cdf1ba5a074df429a9c830769477958a85 /opcodes | |
| parent | a3b3345ae62503982698171bcfce0afe23bd8a31 (diff) | |
Correct disassembly of dot product instructions.
Dot products deviate from the normal disassembly rules for lane indexed
instruction. Their canonical representation is in the form of:
v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote
that these instructions select 4x 1 byte elements instead of a single 1 byte
element.
Previously we were disassembling them following the normal rules, this patch
corrects the disassembly.
gas/
PR gas/22559
* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B.
* gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly.
include/
PR gas/22559
* aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B.
opcodes/
PR gas/22559
* aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to
AARCH64_OPND_QLF_S_4B
* aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to
AARCH64_OPND_QLF_S_4B
* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
* aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 10 | ||||
| -rw-r--r-- | opcodes/aarch64-asm.c | 2 | ||||
| -rw-r--r-- | opcodes/aarch64-dis.c | 2 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 1 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 4 |
5 files changed, 15 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a8b8dba5be..aa31dd3013 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,15 @@ 2017-12-19 Tamar Christina <tamar.christina@arm.com> + PR gas/22559 + * aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to + AARCH64_OPND_QLF_S_4B + * aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to + AARCH64_OPND_QLF_S_4B + * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant. + * aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B. + +2017-12-19 Tamar Christina <tamar.christina@arm.com> + PR gas/22529 * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant. diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 9294910a11..92de737eb1 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -126,7 +126,7 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, unsigned reglane_index = info->reglane.index; switch (info->qualifier) { - case AARCH64_OPND_QLF_S_B: + case AARCH64_OPND_QLF_S_4B: /* L:H */ assert (reglane_index < 4); insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H); diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 8fd1ecfc92..aa38adb902 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -331,7 +331,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, info->qualifier = get_expected_qualifier (inst, info->idx); switch (info->qualifier) { - case AARCH64_OPND_QLF_S_B: + case AARCH64_OPND_QLF_S_4B: /* L:H */ info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); info->reglane.regno &= 0x1f; diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index eac0279553..2cccb0c1d7 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -698,6 +698,7 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] = {4, 1, 0x2, "s", OQK_OPD_VARIANT}, {8, 1, 0x3, "d", OQK_OPD_VARIANT}, {16, 1, 0x4, "q", OQK_OPD_VARIANT}, + {1, 4, 0x0, "4b", OQK_OPD_VARIANT}, {1, 4, 0x0, "4b", OQK_OPD_VARIANT}, {1, 8, 0x0, "8b", OQK_OPD_VARIANT}, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 11587dc573..e38ab20838 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1992,8 +1992,8 @@ /* e.g. UDOT <Vd>.2S, <Vn>.8B, <Vm>.4B[<index>]. */ #define QL_V2DOT \ { \ - QLF3(V_2S, V_8B, S_B),\ - QLF3(V_4S, V_16B, S_B),\ + QLF3(V_2S, V_8B, S_4B),\ + QLF3(V_4S, V_16B, S_4B),\ } /* e.g. SHA512H <Qd>, <Qn>, <Vm>.2D . */ |