diff options
| author | Claudiu Zissulescu <claziss@synopsys.com> | 2016-04-06 16:08:04 +0200 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@synopsys.com> | 2016-04-12 10:21:06 +0200 |
| commit | f36e33dac1a97cca8f79ca8b20cf0fb05f1e25f4 (patch) | |
| tree | 36f13760bc5525172fce20159ffd3500e5ad17fd /opcodes/arc-ext.c | |
| parent | 1c2e355e4830814e18329a53d01cfa634d576211 (diff) | |
Add support for .extCondCode, .extCoreRegister and .extAuxRegister.
gas/
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textauxregister.d: New file.
* testsuite/gas/arc/textauxregister.s: Likewise.
* testsuite/gas/arc/textcondcode.d: Likewise.
* testsuite/gas/arc/textcondcode.s: Likewise.
* testsuite/gas/arc/textcoreregister.d: Likewise.
* testsuite/gas/arc/textcoreregister.s: Likewise.
* testsuite/gas/arc/textpseudoop.d: Likewise.
* testsuite/gas/arc/textpseudoop.s: Likewise.
* testsuite/gas/arc/ld2.d: Update test.
* testsuite/gas/arc/st.d: Likewise.
* testsuite/gas/arc/taux.d: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extCondCode,
.extCoreRegister and .extAuxRegister documentation.
* config/tc-arc.c (arc_extcorereg): New function.
(md_pseudo_table): Add .extCondCode, .extCoreRegister and
.extAuxRegister pseudo-ops.
(extRegister_t): New type.
(ext_condcode, arc_aux_hash): New global variable.
(find_opcode_match): Check for extensions.
(preprocess_operands): Likewise.
(md_begin): Add aux registers in a hash.
(assemble_insn): Update use arc_flags member.
(tokenize_extregister): New function.
(create_extcore_section): Likewise.
* config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Increase to 10.
(arc_flags): Delete code, add flgp.
include/
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (flag_class_t): Update.
(ARC_OPCODE_NONE): Define.
(ARC_OPCODE_ARCALL): Likewise.
(ARC_OPCODE_ARCFPX): Likewise.
(ARC_REGISTER_READONLY): Likewise.
(ARC_REGISTER_WRITEONLY): Likewise.
(ARC_REGISTER_NOSHORT_CUT): Likewise.
(arc_aux_reg): Add cpu.
opcodes/
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (find_format): Check for extension flags.
(print_flags): New function.
(print_insn_arc): Update for .extCondCode, .extCoreRegister and
.extAuxRegister.
* arc-ext.c (arcExtMap_coreRegName): Use
LAST_EXTENSION_CORE_REGISTER.
(arcExtMap_coreReadWrite): Likewise.
(dump_ARC_extmap): Update printing.
* arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
(arc_aux_regs): Add cpu field.
* arc-regs.h: Add cpu field, lower case name aux registers.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
Diffstat (limited to 'opcodes/arc-ext.c')
| -rw-r--r-- | opcodes/arc-ext.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/opcodes/arc-ext.c b/opcodes/arc-ext.c index 45734a0832..1d6381315d 100644 --- a/opcodes/arc-ext.c +++ b/opcodes/arc-ext.c @@ -372,7 +372,7 @@ const char * arcExtMap_coreRegName (int regnum) { if (regnum < FIRST_EXTENSION_CORE_REGISTER - || regnum > LAST_EXTENSION_CONDITION_CODE) + || regnum > LAST_EXTENSION_CORE_REGISTER) return NULL; return arc_extension_map. coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].name; @@ -384,7 +384,7 @@ enum ExtReadWrite arcExtMap_coreReadWrite (int regnum) { if (regnum < FIRST_EXTENSION_CORE_REGISTER - || regnum > LAST_EXTENSION_CONDITION_CODE) + || regnum > LAST_EXTENSION_CORE_REGISTER) return REG_INVALID; return arc_extension_map. coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].rw; @@ -493,8 +493,9 @@ dump_ARC_extmap (void) struct ExtCoreRegister reg = arc_extension_map.coreRegisters[i]; if (reg.name) - printf ("CORE: %s %d %s\n", reg.name, reg.number, - ExtReadWrite_image (reg.rw)); + printf ("CORE: 0x%04x %s %s\n", reg.number, + ExtReadWrite_image (reg.rw), + reg.name); } for (i = 0; i < NUM_EXT_COND; i++) |