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authorJan Beulich <jbeulich@novell.com>2017-11-30 11:48:13 +0100
committerJan Beulich <jbeulich@suse.com>2017-11-30 11:48:13 +0100
commit7ac20022477c163983de77e5b16c016d518ca7bc (patch)
treea8aaf1aa967b6f7892353eb67cf2029e46622d92 /opcodes/ChangeLog
parentb5014f7af26ff0fbc1128b5fabdaf3bd5918dd94 (diff)
x86: derive DispN from BaseIndex
BaseIndex implies - with the exception of string instructions the optional presence of a displacement. This is almost completely uniform for all instructions (the sole exception being MPX ones, which don't allow 16-bit addressing and hence Disp16), so there's no point in explicitly stating this in the main opcode table. Drop those explict specifications in favor of adding logic to i386-gen, shrinking the table size quite a bit and hence making it more readable. The opcodes/i386-tbl.h changes are due to a few cases where pointless Disp* still hadn't been removed from their insns.
Diffstat (limited to 'opcodes/ChangeLog')
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diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 718c485e48..7c4c2b2c32 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,22 @@
2017-11-29 Jan Beulich <jbeulich@suse.com>
+ * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
+ New.
+ (output_cpu_flags): Update active_cpu_flags.
+ (process_i386_opcode_modifier): Update active_isstring.
+ (output_operand_type): Rename "macro" parameter to "stage",
+ changing its type.
+ (process_i386_operand_type): Likewise. Track presence of
+ BaseIndex and emit DispN accordingly.
+ (output_i386_opcode, process_i386_registers,
+ process_i386_initializers): Adjust calls to
+ process_i386_operand_type() for its changed parameter type.
+ * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
+ all insns operands having BaseIndex set.
+ * i386-tbl.h: Re-generate.
+
+2017-11-29 Jan Beulich <jbeulich@suse.com>
+
* i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
entry.
(operand_types): Remove Vec_Disp8 entry.