diff options
| author | Kevin Buettner <kevinb@redhat.com> | 2014-02-03 21:52:59 -0700 |
|---|---|---|
| committer | Kevin Buettner <kevinb@redhat.com> | 2014-02-03 21:52:59 -0700 |
| commit | c5bb736278be60d6d3c0b49a5772991ba42389d6 (patch) | |
| tree | 12940e9b0b9ed74b4fe5e3edba47d9c5d800b48e /gdb/mn10300-tdep.c | |
| parent | f3657eed66a46a4c96c9409d8ff3627c5127da96 (diff) | |
Update mn10300 dwarf register map
This change updates the mn10300 dwarf register map. It reduces the
failure count when doing simulator testing against the default
multilib from 788 to 99.
gdb/ChangeLog:
* mn10300-tdep.c (mn10300_dwarf2_reg_to_regnum): Rewrite
dwarf2_to_gdb[] table using symbolic constants. Adjust
penultimate entry from number representing the PC register
to symbolic constant representing the MDR register. Add
constant for the PC register to the end of the table.
Diffstat (limited to 'gdb/mn10300-tdep.c')
| -rw-r--r-- | gdb/mn10300-tdep.c | 27 |
1 files changed, 20 insertions, 7 deletions
diff --git a/gdb/mn10300-tdep.c b/gdb/mn10300-tdep.c index ac53ae4a8b..10a82627a2 100644 --- a/gdb/mn10300-tdep.c +++ b/gdb/mn10300-tdep.c @@ -1361,13 +1361,26 @@ mn10300_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int dwarf2) appear in GCC's numbering, but have no counterpart in GDB's world, are marked with a -1. */ static int dwarf2_to_gdb[] = { - 0, 1, 2, 3, 4, 5, 6, 7, -1, 8, - 15, 16, 17, 18, 19, 20, 21, 22, - 32, 33, 34, 35, 36, 37, 38, 39, - 40, 41, 42, 43, 44, 45, 46, 47, - 48, 49, 50, 51, 52, 53, 54, 55, - 56, 57, 58, 59, 60, 61, 62, 63, - 9, 11 + E_D0_REGNUM, E_D1_REGNUM, E_D2_REGNUM, E_D3_REGNUM, + E_A0_REGNUM, E_A1_REGNUM, E_A2_REGNUM, E_A3_REGNUM, + -1, E_SP_REGNUM, + + E_E0_REGNUM, E_E1_REGNUM, E_E2_REGNUM, E_E3_REGNUM, + E_E4_REGNUM, E_E5_REGNUM, E_E6_REGNUM, E_E7_REGNUM, + + E_FS0_REGNUM + 0, E_FS0_REGNUM + 1, E_FS0_REGNUM + 2, E_FS0_REGNUM + 3, + E_FS0_REGNUM + 4, E_FS0_REGNUM + 5, E_FS0_REGNUM + 6, E_FS0_REGNUM + 7, + + E_FS0_REGNUM + 8, E_FS0_REGNUM + 9, E_FS0_REGNUM + 10, E_FS0_REGNUM + 11, + E_FS0_REGNUM + 12, E_FS0_REGNUM + 13, E_FS0_REGNUM + 14, E_FS0_REGNUM + 15, + + E_FS0_REGNUM + 16, E_FS0_REGNUM + 17, E_FS0_REGNUM + 18, E_FS0_REGNUM + 19, + E_FS0_REGNUM + 20, E_FS0_REGNUM + 21, E_FS0_REGNUM + 22, E_FS0_REGNUM + 23, + + E_FS0_REGNUM + 24, E_FS0_REGNUM + 25, E_FS0_REGNUM + 26, E_FS0_REGNUM + 27, + E_FS0_REGNUM + 28, E_FS0_REGNUM + 29, E_FS0_REGNUM + 30, E_FS0_REGNUM + 31, + + E_MDR_REGNUM, E_PSW_REGNUM, E_PC_REGNUM }; if (dwarf2 < 0 |