diff options
| author | Yao Qi <yao.qi@linaro.org> | 2015-10-12 11:28:39 +0100 |
|---|---|---|
| committer | Yao Qi <yao.qi@linaro.org> | 2015-10-12 11:28:39 +0100 |
| commit | 1c2e1515c45af104fc9b2aea6bd6b1471238dd98 (patch) | |
| tree | 6d746071c4eb8d9b5fd8cd01d8419754883077cc /gdb/arch | |
| parent | e1c587c312c6347d8f14a019b79e4de0181de599 (diff) | |
Rename emit_load_store to aarch64_emit_load_store
Likewise, this patch renames emit_load_store to
aarch64_emit_load_store.
gdb:
2015-10-12 Yao Qi <yao.qi@linaro.org>
* arch/aarch64-insn.c (emit_load_store): Rename to ...
(aarch64_emit_load_store): ... it. All callers updated.
gdb/gdbserver:
2015-10-12 Yao Qi <yao.qi@linaro.org>
* linux-aarch64-low.c: Update all callers as emit_load_store
is renamed to aarch64_emit_load_store.
Diffstat (limited to 'gdb/arch')
| -rw-r--r-- | gdb/arch/aarch64-insn.c | 10 | ||||
| -rw-r--r-- | gdb/arch/aarch64-insn.h | 14 |
2 files changed, 12 insertions, 12 deletions
diff --git a/gdb/arch/aarch64-insn.c b/gdb/arch/aarch64-insn.c index 99f4fb9fb7..0ec7269819 100644 --- a/gdb/arch/aarch64-insn.c +++ b/gdb/arch/aarch64-insn.c @@ -342,11 +342,11 @@ aarch64_emit_insn (uint32_t *buf, uint32_t insn) /* Helper function emitting a load or store instruction. */ int -emit_load_store (uint32_t *buf, uint32_t size, - enum aarch64_opcodes opcode, - struct aarch64_register rt, - struct aarch64_register rn, - struct aarch64_memory_operand operand) +aarch64_emit_load_store (uint32_t *buf, uint32_t size, + enum aarch64_opcodes opcode, + struct aarch64_register rt, + struct aarch64_register rn, + struct aarch64_memory_operand operand) { uint32_t op; diff --git a/gdb/arch/aarch64-insn.h b/gdb/arch/aarch64-insn.h index 37ef37eeba..d51cabc5cf 100644 --- a/gdb/arch/aarch64-insn.h +++ b/gdb/arch/aarch64-insn.h @@ -269,7 +269,7 @@ void aarch64_relocate_instruction (uint32_t insn, 0 .. 32760 range (12 bits << 3). */ #define emit_ldr(buf, rt, rn, operand) \ - emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand) + aarch64_emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand) /* Write a LDRSW instruction into *BUF. The register size is 64-bit. @@ -283,7 +283,7 @@ void aarch64_relocate_instruction (uint32_t insn, 0 .. 16380 range (12 bits << 2). */ #define emit_ldrsw(buf, rt, rn, operand) \ - emit_load_store (buf, 3, LDRSW, rt, rn, operand) + aarch64_emit_load_store (buf, 3, LDRSW, rt, rn, operand) /* Write a TBZ or TBNZ instruction into *BUF. @@ -312,10 +312,10 @@ void aarch64_relocate_instruction (uint32_t insn, int aarch64_emit_insn (uint32_t *buf, uint32_t insn); -int emit_load_store (uint32_t *buf, uint32_t size, - enum aarch64_opcodes opcode, - struct aarch64_register rt, - struct aarch64_register rn, - struct aarch64_memory_operand operand); +int aarch64_emit_load_store (uint32_t *buf, uint32_t size, + enum aarch64_opcodes opcode, + struct aarch64_register rt, + struct aarch64_register rn, + struct aarch64_memory_operand operand); #endif |