MIPS: Verify the ISA mode and alignment of branch and jump targets

Verify that the ISA mode of branch targets is the same as the referring
relocation, so that an attempt to produce a branch between instructions
encoded in different ISA modes each causes an error rather than silently
producing non-functional code.  Make sure that no symbol or addend bits
are silently truncated: terminate with an error if the relocation value
calculated cannot be encoded in the relocatable field of a branch; for
REL targets also applying to any intermediate addend.

Also make jump target's alignment verification consistent with that for
branches.

This change will require an update to some obscure handcoded assembly
sources which make branches to labels placed at data objects, however
for microMIPS code only.  These labels will have to be updated with the
`.insn' directive for containing code to assemble and link successfully.
Such code is broken as any such labels have always been required by the
microMIPS architecture specification[1][2] to be annotated this way for
correct interpretation, and with our old code missing `.insn' directives
caused labels to present different semantics depending on whether they
were referred with branch (ISA bit ignored) or other relocations (ISA
bit respected).

Enforcing these checks however will ensure errors in building software,
like mixed regular MIPS and microMIPS code links with branches between,
will be diagnosed at the build time rather than causing odd run-time
errors such as intermittent crashes.  It will also let cross-mode BAL
instructions be converted to JALX instructions, with a separate change.

References:

[1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
    Revision 5.04, January 15, 2014, Section 7.1 "Assembly-Level
    Compatibility", p. 533

[2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
    Revision 5.04, January 15, 2014, Section 8.1 "Assembly-Level
    Compatibility", p. 623

	bfd/
	* elfxx-mips.c (b_reloc_p): Add R_MICROMIPS_PC16_S1,
	R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC7_S1.
	(branch_reloc_p): New function.
	(mips_elf_calculate_relocation): Handle ISA mode determination
	for relocations against section symbols, against absolute
	symbols and absolute relocations.  Also set `*cross_mode_jump_p'
	for branches.
	<R_MIPS16_26, R_MIPS_26, R_MICROMIPS_26_S1>: Suppress alignment
	checks for weak undefined symbols.  Also check target alignment
	within the same ISA mode.
	<R_MIPS_PC16, R_MIPS_GNU_REL16_S2>: Handle cross-mode branches
	in the alignment check.
	<R_MICROMIPS_PC7_S1>: Add an alignment check.
	<R_MICROMIPS_PC10_S1>: Likewise.
	<R_MICROMIPS_PC16_S1>: Likewise.
	(mips_elf_perform_relocation): Report a failure for unsupported
	same-mode JALX instructions and cross-mode branches.
	(_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Add
	error messages for jumps to misaligned addresses.

	gas/
	* config/tc-mips.c (mips_force_relocation): Also retain branch
	relocations against MIPS16 and microMIPS symbols.
	(fix_bad_cross_mode_jump_p): New function.
	(fix_bad_same_mode_jalx_p): Likewise.
	(fix_bad_misaligned_jump_p): Likewise.
	(fix_bad_cross_mode_branch_p): Likewise.
	(fix_bad_misaligned_branch_p): Likewise.
	(fix_validate_branch): Likewise.
	(md_apply_fix) <BFD_RELOC_MIPS_JMP, BFD_RELOC_MIPS16_JMP>
	<BFD_RELOC_MICROMIPS_JMP>: Separate from BFD_RELOC_MIPS_SHIFT5,
	etc.  Verify the ISA mode and alignment of the jump target.
	<BFD_RELOC_MIPS_21_PCREL_S2>: Replace the inline alignment check
	with a call to `fix_validate_branch'.
	<BFD_RELOC_MIPS_26_PCREL_S2>: Likewise.
	<BFD_RELOC_16_PCREL_S2>: Likewise.
	<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
	<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Retain the original addend.
	Verify the ISA mode and alignment of the branch target.
	(md_convert_frag): Verify the ISA mode and alignment of resolved
	MIPS16 branch targets.
	* testsuite/gas/mips/branch-misc-1.s: Annotate non-instruction
	branch targets with `.insn'.
	* testsuite/gas/mips/branch-misc-5.s: Likewise.
	* testsuite/gas/mips/micromips@branch-misc-5-64.d: Update
	accordingly.
	* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
	* testsuite/gas/mips/micromips-branch-relax.s: Annotate
	non-instruction branch target with `.insn'.
	* testsuite/gas/mips/micromips.s: Replace microMIPS JALX targets
	with external symbols.
	* testsuite/gas/mips/micromips-insn32.d: Update accordingly.
	* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
	* testsuite/gas/mips/micromips-trap.d: Likewise.
	* testsuite/gas/mips/micromips.d: Likewise.
	* testsuite/gas/mips/mips16.s: Annotate non-instruction branch
	targets with `.insn'.
	* testsuite/gas/mips/mips16.d: Update accordingly.
	* testsuite/gas/mips/mips16-64.d: Likewise.
	* testsuite/gas/mips/mips16-dwarf2.s: Annotate non-instruction
	branch target with `.insn'.
	* testsuite/gas/mips/relax-swap3.s: Likewise.
	* testsuite/gas/mips/branch-local-2.l: New list test.
	* testsuite/gas/mips/branch-local-3.l: New list test.
	* testsuite/gas/mips/branch-local-n32-2.l: New list test.
	* testsuite/gas/mips/branch-local-n32-3.l: New list test.
	* testsuite/gas/mips/branch-local-n64-2.l: New list test.
	* testsuite/gas/mips/branch-local-n64-3.l: New list test.
	* testsuite/gas/mips/unaligned-jump-1.l: New list test.
	* testsuite/gas/mips/unaligned-jump-2.l: New list test.
	* testsuite/gas/mips/unaligned-jump-3.d: New test.
	* testsuite/gas/mips/unaligned-jump-mips16-1.l: New list test.
	* testsuite/gas/mips/unaligned-jump-mips16-2.l: New list test.
	* testsuite/gas/mips/unaligned-jump-mips16-3.d: New test.
	* testsuite/gas/mips/unaligned-jump-micromips-1.l: New list
	test.
	* testsuite/gas/mips/unaligned-jump-micromips-2.l: New list
	test.
	* testsuite/gas/mips/unaligned-jump-micromips-3.d: New test.
	* testsuite/gas/mips/unaligned-branch-1.l: New list test.
	* testsuite/gas/mips/unaligned-branch-2.l: New list test.
	* testsuite/gas/mips/unaligned-branch-3.d: New test.
	* testsuite/gas/mips/unaligned-branch-r6-1.l: New list test.
	* testsuite/gas/mips/unaligned-branch-r6-2.l: New list test.
	* testsuite/gas/mips/unaligned-branch-r6-3.l: New list test.
	* testsuite/gas/mips/unaligned-branch-r6-4.l: New list test.
	* testsuite/gas/mips/unaligned-branch-r6-5.d: New test.
	* testsuite/gas/mips/unaligned-branch-r6-6.d: New test.
	* testsuite/gas/mips/unaligned-branch-mips16-1.l: New list test.
	* testsuite/gas/mips/unaligned-branch-mips16-2.l: New list test.
	* testsuite/gas/mips/unaligned-branch-mips16-3.d: New test.
	* testsuite/gas/mips/unaligned-branch-micromips-1.l: New list
	test.
	* testsuite/gas/mips/unaligned-branch-micromips-2.l: New list
	test.
	* testsuite/gas/mips/unaligned-branch-micromips-3.d: New test.
	* testsuite/gas/mips/branch-local-2.s: New test source.
	* testsuite/gas/mips/branch-local-3.s: New test source.
	* testsuite/gas/mips/branch-local-n32-2.s: New test source.
	* testsuite/gas/mips/branch-local-n32-3.s: New test source.
	* testsuite/gas/mips/branch-local-n64-2.s: New test source.
	* testsuite/gas/mips/branch-local-n64-3.s: New test source.
	* testsuite/gas/mips/unaligned-jump-1.s: New test source.
	* testsuite/gas/mips/unaligned-jump-2.s: New test source.
	* testsuite/gas/mips/unaligned-jump-mips16-1.s: New test source.
	* testsuite/gas/mips/unaligned-jump-mips16-2.s: New test source.
	* testsuite/gas/mips/unaligned-jump-micromips-1.s: New test
	source.
	* testsuite/gas/mips/unaligned-jump-micromips-2.s: New test
	source.
	* testsuite/gas/mips/unaligned-branch-1.s: New test source.
	* testsuite/gas/mips/unaligned-branch-2.s: New test source.
	* testsuite/gas/mips/unaligned-branch-r6-1.s: New test source.
	* testsuite/gas/mips/unaligned-branch-r6-2.s: New test source.
	* testsuite/gas/mips/unaligned-branch-r6-3.s: New test source.
	* testsuite/gas/mips/unaligned-branch-r6-4.s: New test source.
	* testsuite/gas/mips/unaligned-branch-mips16-1.s: New test
	source.
	* testsuite/gas/mips/unaligned-branch-mips16-2.s: New test
	source.
	* testsuite/gas/mips/unaligned-branch-micromips-1.s: New test
	source.
	* testsuite/gas/mips/unaligned-branch-micromips-2.s: New test
	source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/unaligned-jalx-1.d: Update error message
	expected.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d: Likewise.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d:
	Likewise.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d:
	Likewise.
	* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d: Likewise.
	* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d: Likewise.
	* testsuite/ld-mips-elf/undefweak-overflow.s: Add jumps,
	microMIPS BAL and MIPS16 instructions.
	* testsuite/ld-mips-elf/undefweak-overflow.d: Update
	accordingly.
	* testsuite/ld-mips-elf/unaligned-branch-2.d: New test.
	* testsuite/ld-mips-elf/unaligned-branch-r6-1.d: New test.
	* testsuite/ld-mips-elf/unaligned-branch-r6-2.d: New test.
	* testsuite/ld-mips-elf/unaligned-branch-mips16.d: New test.
	* testsuite/ld-mips-elf/unaligned-branch-micromips.d: New test.
	* testsuite/ld-mips-elf/unaligned-jump-mips16.d: New test.
	* testsuite/ld-mips-elf/unaligned-jump-micromips.d: New test.
	* testsuite/ld-mips-elf/unaligned-jump.d: New test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.

1 files changed, 105 insertions, 13 deletions

diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index e47276bc61..fa99c9dc07 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -2227,7 +2227,10 @@ b_reloc_p (int r_type)
 	  || r_type == R_MIPS_PC21_S2
 	  || r_type == R_MIPS_PC16
 	  || r_type == R_MIPS_GNU_REL16_S2
-	  || r_type == R_MIPS16_PC16_S1);
+	  || r_type == R_MIPS16_PC16_S1
+	  || r_type == R_MICROMIPS_PC16_S1
+	  || r_type == R_MICROMIPS_PC10_S1
+	  || r_type == R_MICROMIPS_PC7_S1);
 }
 
 static inline bfd_boolean
@@ -2238,6 +2241,16 @@ aligned_pcrel_reloc_p (int r_type)
 }
 
 static inline bfd_boolean
+branch_reloc_p (int r_type)
+{
+  return (r_type == R_MIPS_26
+	  || r_type == R_MIPS_PC26_S2
+	  || r_type == R_MIPS_PC21_S2
+	  || r_type == R_MIPS_PC16
+	  || r_type == R_MIPS_GNU_REL16_S2);
+}
+
+static inline bfd_boolean
 mips16_branch_reloc_p (int r_type)
 {
   return (r_type == R_MIPS16_26
@@ -5322,6 +5335,7 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
   /* Figure out the value of the symbol.  */
   if (local_p)
     {
+      bfd_boolean micromips_p = MICROMIPS_P (abfd);
       Elf_Internal_Sym *sym;
 
       sym = local_syms + r_symndx;
@@ -5350,8 +5364,26 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
       if (*namep == NULL || **namep == '\0')
 	*namep = bfd_section_name (input_bfd, sec);
 
-      target_is_16_bit_code_p = ELF_ST_IS_MIPS16 (sym->st_other);
-      target_is_micromips_code_p = ELF_ST_IS_MICROMIPS (sym->st_other);
+      /* For relocations against a section symbol and ones against no
+         symbol (absolute relocations) infer the ISA mode from the addend.  */
+      if (section_p || r_symndx == STN_UNDEF)
+	{
+	  target_is_16_bit_code_p = (addend & 1) && !micromips_p;
+	  target_is_micromips_code_p = (addend & 1) && micromips_p;
+	}
+      /* For relocations against an absolute symbol infer the ISA mode
+         from the value of the symbol plus addend.  */
+      else if (bfd_is_abs_section (sec))
+	{
+	  target_is_16_bit_code_p = ((symbol + addend) & 1) && !micromips_p;
+	  target_is_micromips_code_p = ((symbol + addend) & 1) && micromips_p;
+	}
+      /* Otherwise just use the regular symbol annotation available.  */
+      else
+	{
+	  target_is_16_bit_code_p = ELF_ST_IS_MIPS16 (sym->st_other);
+	  target_is_micromips_code_p = ELF_ST_IS_MICROMIPS (sym->st_other);
+	}
     }
   else
     {
@@ -5591,10 +5623,12 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
      acceptable.  */
   *cross_mode_jump_p = (!bfd_link_relocatable (info)
 			&& !(h && h->root.root.type == bfd_link_hash_undefweak)
-			&& ((r_type == R_MIPS16_26 && !target_is_16_bit_code_p)
-			    || (r_type == R_MICROMIPS_26_S1
+			&& ((mips16_branch_reloc_p (r_type)
+			     && !target_is_16_bit_code_p)
+			    || (micromips_branch_reloc_p (r_type)
 				&& !target_is_micromips_code_p)
-			    || ((r_type == R_MIPS_26 || r_type == R_MIPS_JALR)
+			    || ((branch_reloc_p (r_type)
+				 || r_type == R_MIPS_JALR)
 				&& (target_is_16_bit_code_p
 				    || target_is_micromips_code_p))));
 
@@ -5804,9 +5838,13 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
 	  value = addend;
 	value += symbol;
 
-	/* Make sure the target of JALX is word-aligned.  Bit 0 must be
-	   the correct ISA mode selector and bit 1 must be 0.  */
-	if (*cross_mode_jump_p && (value & 3) != (r_type == R_MIPS_26))
+	/* Make sure the target of a jump is suitably aligned.  Bit 0 must
+	   be the correct ISA mode selector except for weak undefined
+	   symbols.  */
+	if ((was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+	    && (*cross_mode_jump_p
+		? (value & 3) != (r_type == R_MIPS_26)
+	        : (value & ((1 << shift) - 1)) != (r_type != R_MIPS_26)))
 	  return bfd_reloc_outofrange;
 
 	value >>= shift;
@@ -5997,7 +6035,12 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
       if (howto->partial_inplace)
 	addend = _bfd_mips_elf_sign_extend (addend, 18);
 
-      if ((symbol + addend) & 3)
+      /* No need to exclude weak undefined symbols here as they resolve
+         to 0 and never set `*cross_mode_jump_p', so this alignment check
+         will never trigger for them.  */
+      if (*cross_mode_jump_p
+	  ? ((symbol + addend) & 3) != 1
+	  : ((symbol + addend) & 3) != 0)
 	return bfd_reloc_outofrange;
 
       value = symbol + addend - p;
@@ -6012,7 +6055,9 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
 	addend = _bfd_mips_elf_sign_extend (addend, 17);
 
       if ((was_local_p || h->root.root.type != bfd_link_hash_undefweak)
-	  && ((symbol + addend) & 1) == 0)
+	  && (*cross_mode_jump_p
+	      ? ((symbol + addend) & 3) != 0
+	      : ((symbol + addend) & 1) == 0))
 	return bfd_reloc_outofrange;
 
       value = symbol + addend - p;
@@ -6095,6 +6140,13 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
     case R_MICROMIPS_PC7_S1:
       if (howto->partial_inplace)
 	addend = _bfd_mips_elf_sign_extend (addend, 8);
+
+      if ((was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+	  && (*cross_mode_jump_p
+	      ? ((symbol + addend + 2) & 3) != 0
+	      : ((symbol + addend + 2) & 1) == 0))
+	return bfd_reloc_outofrange;
+
       value = symbol + addend - p;
       if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
 	overflowed_p = mips_elf_overflow_p (value, 8);
@@ -6105,6 +6157,13 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
     case R_MICROMIPS_PC10_S1:
       if (howto->partial_inplace)
 	addend = _bfd_mips_elf_sign_extend (addend, 11);
+
+      if ((was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+	  && (*cross_mode_jump_p
+	      ? ((symbol + addend + 2) & 3) != 0
+	      : ((symbol + addend + 2) & 1) == 0))
+	return bfd_reloc_outofrange;
+
       value = symbol + addend - p;
       if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
 	overflowed_p = mips_elf_overflow_p (value, 11);
@@ -6115,6 +6174,13 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
     case R_MICROMIPS_PC16_S1:
       if (howto->partial_inplace)
 	addend = _bfd_mips_elf_sign_extend (addend, 17);
+
+      if ((was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+	  && (*cross_mode_jump_p
+	      ? ((symbol + addend) & 3) != 0
+	      : ((symbol + addend) & 1) == 0))
+	return bfd_reloc_outofrange;
+
       value = symbol + addend - p;
       if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
 	overflowed_p = mips_elf_overflow_p (value, 17);
@@ -6273,7 +6339,21 @@ mips_elf_perform_relocation (struct bfd_link_info *info,
   /* Set the field.  */
   x |= (value & howto->dst_mask);
 
-  /* If required, turn JAL into JALX.  */
+  /* Detect incorrect JALX usage.  If required, turn JAL into JALX.  */
+  if (!cross_mode_jump_p && jal_reloc_p (r_type))
+    {
+      bfd_vma opcode = x >> 26;
+
+      if (r_type == R_MIPS16_26 ? opcode == 0x7
+	  : r_type == R_MICROMIPS_26_S1 ? opcode == 0x3c
+	  : opcode == 0x1d)
+	{
+	  info->callbacks->einfo
+	    (_("%X%H: Unsupported JALX to the same ISA mode\n"),
+	     input_bfd, input_section, relocation->r_offset);
+	  return TRUE;
+	}
+    }
   if (cross_mode_jump_p && jal_reloc_p (r_type))
     {
       bfd_boolean ok;
@@ -6311,6 +6391,13 @@ mips_elf_perform_relocation (struct bfd_link_info *info,
       /* Make this the JALX opcode.  */
       x = (x & ~(0x3f << 26)) | (jalx_opcode << 26);
     }
+  else if (cross_mode_jump_p && b_reloc_p (r_type))
+    {
+      info->callbacks->einfo
+	(_("%X%H: Unsupported branch between ISA modes\n"),
+	 input_bfd, input_section, relocation->r_offset);
+      return TRUE;
+    }
 
   /* Try converting JAL to BAL and J(AL)R to B(AL), if the target is in
      range.  */
@@ -10296,7 +10383,12 @@ _bfd_mips_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	case bfd_reloc_outofrange:
 	  msg = NULL;
 	  if (jal_reloc_p (howto->type))
-	    msg = _("JALX to a non-word-aligned address");
+	    msg = (cross_mode_jump_p
+		   ? _("Cannot convert a jump to JALX "
+		       "for a non-word-aligned address")
+		   : (howto->type == R_MIPS16_26
+		      ? _("Jump to a non-word-aligned address")
+		      : _("Jump to a non-instruction-aligned address")));
 	  else if (b_reloc_p (howto->type))
 	    msg = _("Branch to a non-instruction-aligned address");
 	  else if (aligned_pcrel_reloc_p (howto->type))