Enable Intel AVX512_VNNI instructions.

Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .avx512_vnni.
	(cpu_noarch): Add noavx512_vnni.
	* doc/c-i386.texi: Document .avx512_vnni.
	* testsuite/gas/i386/i386.exp: Add AVX512_VNNI tests.
	* testsuite/gas/i386/avx512vnni-intel.d: New test.
	* testsuite/gas/i386/avx512vnni.d: Likewise.
	* testsuite/gas/i386/avx512vnni.s: Likewise.
	* testsuite/gas/i386/avx512vnni_vl-intel.d: Likewise.
	* testsuite/gas/i386/avx512vnni_vl.d: Likewise.
	* testsuite/gas/i386/avx512vnni_vl.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni_vl-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni_vl.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni_vl.s: Likewise.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
	CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_VNNI.
	* i386-opc.h (enum): Add CpuAVX512_VNNI.
	(i386_cpu_flags): Add cpuavx512_vnni.
	* i386-opc.tbl Add Intel AVX512_VNNI instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.

20 files changed, 1025 insertions, 7 deletions

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index f4b86f6bf1..1f2efdc9e6 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -984,6 +984,8 @@ static const arch_entry cpu_arch[] =
     CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
   { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
     CPU_AVX512_VBMI2_FLAGS, 0 },
+  { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
+    CPU_AVX512_VNNI_FLAGS, 0 },
   { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
     CPU_CLZERO_FLAGS, 0 },
   { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
@@ -1033,6 +1035,7 @@ static const noarch_entry cpu_noarch[] =
   { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
   { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
   { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
+  { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
 };
 
 #ifdef I386COFF
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 44ade83517..f2e8f4ee4d 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -188,6 +188,7 @@ accept various extension mnemonics.  For example,
 @code{avx512_4vnniw},
 @code{avx512_vpopcntdq},
 @code{avx512_vbmi2},
+@code{avx512_vnni},
 @code{noavx512f},
 @code{noavx512cd},
 @code{noavx512er},
@@ -201,6 +202,7 @@ accept various extension mnemonics.  For example,
 @code{noavx512_4vnniw},
 @code{noavx512_vpopcntdq},
 @code{noavx512_vbmi2},
+@code{noavx512_vnni},
 @code{vmx},
 @code{vmfunc},
 @code{smx},
@@ -1223,7 +1225,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
-@item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2}
+@item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.cet}
 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
diff --git a/gas/testsuite/gas/i386/avx512vnni-intel.d b/gas/testsuite/gas/i386/avx512vnni-intel.d
new file mode 100644
index 0000000000..b2ac448b2e
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vnni-intel.d
@@ -0,0 +1,60 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 AVX512VNNI insns (Intel disassembly)
+#source: avx512vnni.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 52 e3[ 	]*vpdpwssd zmm4,zmm1,zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 49 52 e3[ 	]*vpdpwssd zmm4\{k1\},zmm1,zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 c9 52 e3[ 	]*vpdpwssd zmm4\{k1\}\{z\},zmm1,zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 52 a4 f4 c0 1d fe ff[ 	]*vpdpwssd zmm4,zmm1,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 52 62 7f[ 	]*vpdpwssd zmm4,zmm1,ZMMWORD PTR \[edx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 58 52 62 7f[ 	]*vpdpwssd zmm4,zmm1,DWORD PTR \[edx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 48 53 d4[ 	]*vpdpwssds zmm2,zmm5,zmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 4e 53 d4[ 	]*vpdpwssds zmm2\{k6\},zmm5,zmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 ce 53 d4[ 	]*vpdpwssds zmm2\{k6\}\{z\},zmm5,zmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 48 53 94 f4 c0 1d fe ff[ 	]*vpdpwssds zmm2,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 48 53 52 7f[ 	]*vpdpwssds zmm2,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 58 53 52 7f[ 	]*vpdpwssds zmm2,zmm5,DWORD PTR \[edx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 48 50 eb[ 	]*vpdpbusd zmm5,zmm2,zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 49 50 eb[ 	]*vpdpbusd zmm5\{k1\},zmm2,zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d c9 50 eb[ 	]*vpdpbusd zmm5\{k1\}\{z\},zmm2,zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 48 50 ac f4 c0 1d fe ff[ 	]*vpdpbusd zmm5,zmm2,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 48 50 6a 7f[ 	]*vpdpbusd zmm5,zmm2,ZMMWORD PTR \[edx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 58 50 6a 7f[ 	]*vpdpbusd zmm5,zmm2,DWORD PTR \[edx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 48 51 e9[ 	]*vpdpbusds zmm5,zmm3,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 4a 51 e9[ 	]*vpdpbusds zmm5\{k2\},zmm3,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 ca 51 e9[ 	]*vpdpbusds zmm5\{k2\}\{z\},zmm3,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 48 51 ac f4 c0 1d fe ff[ 	]*vpdpbusds zmm5,zmm3,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 48 51 6a 7f[ 	]*vpdpbusds zmm5,zmm3,ZMMWORD PTR \[edx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 58 51 6a 7f[ 	]*vpdpbusds zmm5,zmm3,DWORD PTR \[edx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 48 52 d9[ 	]*vpdpwssd zmm3,zmm4,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 4b 52 d9[ 	]*vpdpwssd zmm3\{k3\},zmm4,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d cb 52 d9[ 	]*vpdpwssd zmm3\{k3\}\{z\},zmm4,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 48 52 9c f4 c0 1d fe ff[ 	]*vpdpwssd zmm3,zmm4,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 48 52 5a 7f[ 	]*vpdpwssd zmm3,zmm4,ZMMWORD PTR \[edx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 58 52 5a 7f[ 	]*vpdpwssd zmm3,zmm4,DWORD PTR \[edx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 53 da[ 	]*vpdpwssds zmm3,zmm1,zmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 4f 53 da[ 	]*vpdpwssds zmm3\{k7\},zmm1,zmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 cf 53 da[ 	]*vpdpwssds zmm3\{k7\}\{z\},zmm1,zmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 53 9c f4 c0 1d fe ff[ 	]*vpdpwssds zmm3,zmm1,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 53 5a 7f[ 	]*vpdpwssds zmm3,zmm1,ZMMWORD PTR \[edx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 58 53 5a 7f[ 	]*vpdpwssds zmm3,zmm1,DWORD PTR \[edx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 48 50 d9[ 	]*vpdpbusd zmm3,zmm4,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 4e 50 d9[ 	]*vpdpbusd zmm3\{k6\},zmm4,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d ce 50 d9[ 	]*vpdpbusd zmm3\{k6\}\{z\},zmm4,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 48 50 9c f4 c0 1d fe ff[ 	]*vpdpbusd zmm3,zmm4,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 48 50 5a 7f[ 	]*vpdpbusd zmm3,zmm4,ZMMWORD PTR \[edx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 58 50 5a 7f[ 	]*vpdpbusd zmm3,zmm4,DWORD PTR \[edx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 51 c9[ 	]*vpdpbusds zmm1,zmm1,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 49 51 c9[ 	]*vpdpbusds zmm1\{k1\},zmm1,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 c9 51 c9[ 	]*vpdpbusds zmm1\{k1\}\{z\},zmm1,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 51 8c f4 c0 1d fe ff[ 	]*vpdpbusds zmm1,zmm1,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 51 4a 7f[ 	]*vpdpbusds zmm1,zmm1,ZMMWORD PTR \[edx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 58 51 4a 7f[ 	]*vpdpbusds zmm1,zmm1,DWORD PTR \[edx\+0x1fc\]\{1to16\}
+#pass
diff --git a/gas/testsuite/gas/i386/avx512vnni.d b/gas/testsuite/gas/i386/avx512vnni.d
new file mode 100644
index 0000000000..353dfcf922
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vnni.d
@@ -0,0 +1,60 @@
+#as:
+#objdump: -dw
+#name: i386 AVX512VNNI insns
+#source: avx512vnni.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 52 e3[ 	]*vpdpwssd %zmm3,%zmm1,%zmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 49 52 e3[ 	]*vpdpwssd %zmm3,%zmm1,%zmm4\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 c9 52 e3[ 	]*vpdpwssd %zmm3,%zmm1,%zmm4\{%k1\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 52 a4 f4 c0 1d fe ff[ 	]*vpdpwssd -0x1e240\(%esp,%esi,8\),%zmm1,%zmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 52 62 7f[ 	]*vpdpwssd 0x1fc0\(%edx\),%zmm1,%zmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 58 52 62 7f[ 	]*vpdpwssd 0x1fc\(%edx\)\{1to16\},%zmm1,%zmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 48 53 d4[ 	]*vpdpwssds %zmm4,%zmm5,%zmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 4e 53 d4[ 	]*vpdpwssds %zmm4,%zmm5,%zmm2\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 ce 53 d4[ 	]*vpdpwssds %zmm4,%zmm5,%zmm2\{%k6\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 48 53 94 f4 c0 1d fe ff[ 	]*vpdpwssds -0x1e240\(%esp,%esi,8\),%zmm5,%zmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 48 53 52 7f[ 	]*vpdpwssds 0x1fc0\(%edx\),%zmm5,%zmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 58 53 52 7f[ 	]*vpdpwssds 0x1fc\(%edx\)\{1to16\},%zmm5,%zmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 48 50 eb[ 	]*vpdpbusd %zmm3,%zmm2,%zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 49 50 eb[ 	]*vpdpbusd %zmm3,%zmm2,%zmm5\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d c9 50 eb[ 	]*vpdpbusd %zmm3,%zmm2,%zmm5\{%k1\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 48 50 ac f4 c0 1d fe ff[ 	]*vpdpbusd -0x1e240\(%esp,%esi,8\),%zmm2,%zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 48 50 6a 7f[ 	]*vpdpbusd 0x1fc0\(%edx\),%zmm2,%zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 58 50 6a 7f[ 	]*vpdpbusd 0x1fc\(%edx\)\{1to16\},%zmm2,%zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 48 51 e9[ 	]*vpdpbusds %zmm1,%zmm3,%zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 4a 51 e9[ 	]*vpdpbusds %zmm1,%zmm3,%zmm5\{%k2\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 ca 51 e9[ 	]*vpdpbusds %zmm1,%zmm3,%zmm5\{%k2\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 48 51 ac f4 c0 1d fe ff[ 	]*vpdpbusds -0x1e240\(%esp,%esi,8\),%zmm3,%zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 48 51 6a 7f[ 	]*vpdpbusds 0x1fc0\(%edx\),%zmm3,%zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 58 51 6a 7f[ 	]*vpdpbusds 0x1fc\(%edx\)\{1to16\},%zmm3,%zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 48 52 d9[ 	]*vpdpwssd %zmm1,%zmm4,%zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 4b 52 d9[ 	]*vpdpwssd %zmm1,%zmm4,%zmm3\{%k3\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d cb 52 d9[ 	]*vpdpwssd %zmm1,%zmm4,%zmm3\{%k3\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 48 52 9c f4 c0 1d fe ff[ 	]*vpdpwssd -0x1e240\(%esp,%esi,8\),%zmm4,%zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 48 52 5a 7f[ 	]*vpdpwssd 0x1fc0\(%edx\),%zmm4,%zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 58 52 5a 7f[ 	]*vpdpwssd 0x1fc\(%edx\)\{1to16\},%zmm4,%zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 53 da[ 	]*vpdpwssds %zmm2,%zmm1,%zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 4f 53 da[ 	]*vpdpwssds %zmm2,%zmm1,%zmm3\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 cf 53 da[ 	]*vpdpwssds %zmm2,%zmm1,%zmm3\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 53 9c f4 c0 1d fe ff[ 	]*vpdpwssds -0x1e240\(%esp,%esi,8\),%zmm1,%zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 53 5a 7f[ 	]*vpdpwssds 0x1fc0\(%edx\),%zmm1,%zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 58 53 5a 7f[ 	]*vpdpwssds 0x1fc\(%edx\)\{1to16\},%zmm1,%zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 48 50 d9[ 	]*vpdpbusd %zmm1,%zmm4,%zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 4e 50 d9[ 	]*vpdpbusd %zmm1,%zmm4,%zmm3\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d ce 50 d9[ 	]*vpdpbusd %zmm1,%zmm4,%zmm3\{%k6\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 48 50 9c f4 c0 1d fe ff[ 	]*vpdpbusd -0x1e240\(%esp,%esi,8\),%zmm4,%zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 48 50 5a 7f[ 	]*vpdpbusd 0x1fc0\(%edx\),%zmm4,%zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 58 50 5a 7f[ 	]*vpdpbusd 0x1fc\(%edx\)\{1to16\},%zmm4,%zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 51 c9[ 	]*vpdpbusds %zmm1,%zmm1,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 49 51 c9[ 	]*vpdpbusds %zmm1,%zmm1,%zmm1\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 c9 51 c9[ 	]*vpdpbusds %zmm1,%zmm1,%zmm1\{%k1\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 51 8c f4 c0 1d fe ff[ 	]*vpdpbusds -0x1e240\(%esp,%esi,8\),%zmm1,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 51 4a 7f[ 	]*vpdpbusds 0x1fc0\(%edx\),%zmm1,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 58 51 4a 7f[ 	]*vpdpbusds 0x1fc\(%edx\)\{1to16\},%zmm1,%zmm1
+#pass
diff --git a/gas/testsuite/gas/i386/avx512vnni.s b/gas/testsuite/gas/i386/avx512vnni.s
new file mode 100644
index 0000000000..b197613372
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vnni.s
@@ -0,0 +1,60 @@
+# Check 32bit AVX512VNNI instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vpdpwssd	%zmm3, %zmm1, %zmm4	 # AVX512VNNI
+	vpdpwssd	%zmm3, %zmm1, %zmm4{%k1}	 # AVX512VNNI
+	vpdpwssd	%zmm3, %zmm1, %zmm4{%k1}{z}	 # AVX512VNNI
+	vpdpwssd	-123456(%esp,%esi,8), %zmm1, %zmm4	 # AVX512VNNI
+	vpdpwssd	8128(%edx), %zmm1, %zmm4	 # AVX512VNNI Disp8
+	vpdpwssd	508(%edx){1to16}, %zmm1, %zmm4	 # AVX512VNNI Disp8
+
+	vpdpwssds	%zmm4, %zmm5, %zmm2	 # AVX512VNNI
+	vpdpwssds	%zmm4, %zmm5, %zmm2{%k6}	 # AVX512VNNI
+	vpdpwssds	%zmm4, %zmm5, %zmm2{%k6}{z}	 # AVX512VNNI
+	vpdpwssds	-123456(%esp,%esi,8), %zmm5, %zmm2	 # AVX512VNNI
+	vpdpwssds	8128(%edx), %zmm5, %zmm2	 # AVX512VNNI Disp8
+	vpdpwssds	508(%edx){1to16}, %zmm5, %zmm2	 # AVX512VNNI Disp8
+
+	vpdpbusd	%zmm3, %zmm2, %zmm5	 # AVX512VNNI
+	vpdpbusd	%zmm3, %zmm2, %zmm5{%k1}	 # AVX512VNNI
+	vpdpbusd	%zmm3, %zmm2, %zmm5{%k1}{z}	 # AVX512VNNI
+	vpdpbusd	-123456(%esp,%esi,8), %zmm2, %zmm5	 # AVX512VNNI
+	vpdpbusd	8128(%edx), %zmm2, %zmm5	 # AVX512VNNI Disp8
+	vpdpbusd	508(%edx){1to16}, %zmm2, %zmm5	 # AVX512VNNI Disp8
+
+	vpdpbusds	%zmm1, %zmm3, %zmm5	 # AVX512VNNI
+	vpdpbusds	%zmm1, %zmm3, %zmm5{%k2}	 # AVX512VNNI
+	vpdpbusds	%zmm1, %zmm3, %zmm5{%k2}{z}	 # AVX512VNNI
+	vpdpbusds	-123456(%esp,%esi,8), %zmm3, %zmm5	 # AVX512VNNI
+	vpdpbusds	8128(%edx), %zmm3, %zmm5	 # AVX512VNNI Disp8
+	vpdpbusds	508(%edx){1to16}, %zmm3, %zmm5	 # AVX512VNNI Disp8
+
+	.intel_syntax noprefix
+	vpdpwssd	zmm3, zmm4, zmm1	 # AVX512VNNI
+	vpdpwssd	zmm3{k3}, zmm4, zmm1	 # AVX512VNNI
+	vpdpwssd	zmm3{k3}{z}, zmm4, zmm1	 # AVX512VNNI
+	vpdpwssd	zmm3, zmm4, ZMMWORD PTR [esp+esi*8-123456]	 # AVX512VNNI
+	vpdpwssd	zmm3, zmm4, ZMMWORD PTR [edx+8128]	 # AVX512VNNI Disp8
+	vpdpwssd	zmm3, zmm4, [edx+508]{1to16}	 # AVX512VNNI Disp8
+
+	vpdpwssds	zmm3, zmm1, zmm2	 # AVX512VNNI
+	vpdpwssds	zmm3{k7}, zmm1, zmm2	 # AVX512VNNI
+	vpdpwssds	zmm3{k7}{z}, zmm1, zmm2	 # AVX512VNNI
+	vpdpwssds	zmm3, zmm1, ZMMWORD PTR [esp+esi*8-123456]	 # AVX512VNNI
+	vpdpwssds	zmm3, zmm1, ZMMWORD PTR [edx+8128]	 # AVX512VNNI Disp8
+	vpdpwssds	zmm3, zmm1, [edx+508]{1to16}	 # AVX512VNNI Disp8
+
+	vpdpbusd	zmm3, zmm4, zmm1	 # AVX512VNNI
+	vpdpbusd	zmm3{k6}, zmm4, zmm1	 # AVX512VNNI
+	vpdpbusd	zmm3{k6}{z}, zmm4, zmm1	 # AVX512VNNI
+	vpdpbusd	zmm3, zmm4, ZMMWORD PTR [esp+esi*8-123456]	 # AVX512VNNI
+	vpdpbusd	zmm3, zmm4, ZMMWORD PTR [edx+8128]	 # AVX512VNNI Disp8
+	vpdpbusd	zmm3, zmm4, [edx+508]{1to16}	 # AVX512VNNI Disp8
+	vpdpbusds	zmm1, zmm1, zmm1	 # AVX512VNNI
+	vpdpbusds	zmm1{k1}, zmm1, zmm1	 # AVX512VNNI
+	vpdpbusds	zmm1{k1}{z}, zmm1, zmm1	 # AVX512VNNI
+	vpdpbusds	zmm1, zmm1, ZMMWORD PTR [esp+esi*8-123456]	 # AVX512VNNI
+	vpdpbusds	zmm1, zmm1, ZMMWORD PTR [edx+8128]	 # AVX512VNNI Disp8
+	vpdpbusds	zmm1, zmm1, [edx+508]{1to16}	 # AVX512VNNI Disp8
diff --git a/gas/testsuite/gas/i386/avx512vnni_vl-intel.d b/gas/testsuite/gas/i386/avx512vnni_vl-intel.d
new file mode 100644
index 0000000000..5a8c8c498a
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vnni_vl-intel.d
@@ -0,0 +1,92 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 AVX512VNNI/VL insns (Intel disassembly)
+#source: avx512vnni_vl.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 0b 52 d2[ 	]*vpdpwssd xmm2\{k3\},xmm4,xmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 8b 52 d2[ 	]*vpdpwssd xmm2\{k3\}\{z\},xmm4,xmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 09 52 94 f4 c0 1d fe ff[ 	]*vpdpwssd xmm2\{k1\},xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 09 52 52 7f[ 	]*vpdpwssd xmm2\{k1\},xmm4,XMMWORD PTR \[edx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 19 52 52 7f[ 	]*vpdpwssd xmm2\{k1\},xmm4,DWORD PTR \[edx\+0x1fc\]\{1to4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 29 52 d9[ 	]*vpdpwssd ymm3\{k1\},ymm3,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 a9 52 d9[ 	]*vpdpwssd ymm3\{k1\}\{z\},ymm3,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 2c 52 9c f4 c0 1d fe ff[ 	]*vpdpwssd ymm3\{k4\},ymm3,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 2c 52 5a 7f[ 	]*vpdpwssd ymm3\{k4\},ymm3,YMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 3c 52 5a 7f[ 	]*vpdpwssd ymm3\{k4\},ymm3,DWORD PTR \[edx\+0x1fc\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 09 53 d1[ 	]*vpdpwssds xmm2\{k1\},xmm4,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 89 53 d1[ 	]*vpdpwssds xmm2\{k1\}\{z\},xmm4,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 0c 53 94 f4 c0 1d fe ff[ 	]*vpdpwssds xmm2\{k4\},xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 0c 53 52 7f[ 	]*vpdpwssds xmm2\{k4\},xmm4,XMMWORD PTR \[edx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 1c 53 52 7f[ 	]*vpdpwssds xmm2\{k4\},xmm4,DWORD PTR \[edx\+0x1fc\]\{1to4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 2f 53 e4[ 	]*vpdpwssds ymm4\{k7\},ymm1,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 af 53 e4[ 	]*vpdpwssds ymm4\{k7\}\{z\},ymm1,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 2b 53 a4 f4 c0 1d fe ff[ 	]*vpdpwssds ymm4\{k3\},ymm1,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 2b 53 62 7f[ 	]*vpdpwssds ymm4\{k3\},ymm1,YMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 3b 53 62 7f[ 	]*vpdpwssds ymm4\{k3\},ymm1,DWORD PTR \[edx\+0x1fc\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 0c 50 d1[ 	]*vpdpbusd xmm2\{k4\},xmm3,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 8c 50 d1[ 	]*vpdpbusd xmm2\{k4\}\{z\},xmm3,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 0a 50 94 f4 c0 1d fe ff[ 	]*vpdpbusd xmm2\{k2\},xmm3,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 0a 50 52 7f[ 	]*vpdpbusd xmm2\{k2\},xmm3,XMMWORD PTR \[edx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 1a 50 52 7f[ 	]*vpdpbusd xmm2\{k2\},xmm3,DWORD PTR \[edx\+0x1fc\]\{1to4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2d 50 d2[ 	]*vpdpbusd ymm2\{k5\},ymm2,ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d ad 50 d2[ 	]*vpdpbusd ymm2\{k5\}\{z\},ymm2,ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2f 50 94 f4 c0 1d fe ff[ 	]*vpdpbusd ymm2\{k7\},ymm2,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2f 50 52 7f[ 	]*vpdpbusd ymm2\{k7\},ymm2,YMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 3f 50 52 7f[ 	]*vpdpbusd ymm2\{k7\},ymm2,DWORD PTR \[edx\+0x1fc\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 0e 51 f4[ 	]*vpdpbusds xmm6\{k6\},xmm2,xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 8e 51 f4[ 	]*vpdpbusds xmm6\{k6\}\{z\},xmm2,xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 0c 51 b4 f4 c0 1d fe ff[ 	]*vpdpbusds xmm6\{k4\},xmm2,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 0c 51 72 7f[ 	]*vpdpbusds xmm6\{k4\},xmm2,XMMWORD PTR \[edx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 1c 51 72 7f[ 	]*vpdpbusds xmm6\{k4\},xmm2,DWORD PTR \[edx\+0x1fc\]\{1to4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 2f 51 e1[ 	]*vpdpbusds ymm4\{k7\},ymm3,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 af 51 e1[ 	]*vpdpbusds ymm4\{k7\}\{z\},ymm3,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 29 51 a4 f4 c0 1d fe ff[ 	]*vpdpbusds ymm4\{k1\},ymm3,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 29 51 62 7f[ 	]*vpdpbusds ymm4\{k1\},ymm3,YMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 39 51 62 7f[ 	]*vpdpbusds ymm4\{k1\},ymm3,DWORD PTR \[edx\+0x1fc\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 09 52 ea[ 	]*vpdpwssd xmm5\{k1\},xmm2,xmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 89 52 ea[ 	]*vpdpwssd xmm5\{k1\}\{z\},xmm2,xmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 0e 52 ac f4 c0 1d fe ff[ 	]*vpdpwssd xmm5\{k6\},xmm2,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 0e 52 6a 7f[ 	]*vpdpwssd xmm5\{k6\},xmm2,XMMWORD PTR \[edx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 1e 52 6a 7f[ 	]*vpdpwssd xmm5\{k6\},xmm2,DWORD PTR \[edx\+0x1fc\]\{1to4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2f 52 cc[ 	]*vpdpwssd ymm1\{k7\},ymm2,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d af 52 cc[ 	]*vpdpwssd ymm1\{k7\}\{z\},ymm2,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2e 52 8c f4 c0 1d fe ff[ 	]*vpdpwssd ymm1\{k6\},ymm2,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2e 52 4a 7f[ 	]*vpdpwssd ymm1\{k6\},ymm2,YMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 3e 52 4a 7f[ 	]*vpdpwssd ymm1\{k6\},ymm2,DWORD PTR \[edx\+0x1fc\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 0a 53 c9[ 	]*vpdpwssds xmm1\{k2\},xmm4,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 8a 53 c9[ 	]*vpdpwssds xmm1\{k2\}\{z\},xmm4,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 0e 53 8c f4 c0 1d fe ff[ 	]*vpdpwssds xmm1\{k6\},xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 0e 53 4a 7f[ 	]*vpdpwssds xmm1\{k6\},xmm4,XMMWORD PTR \[edx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 1e 53 4a 7f[ 	]*vpdpwssds xmm1\{k6\},xmm4,DWORD PTR \[edx\+0x1fc\]\{1to4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2c 53 dc[ 	]*vpdpwssds ymm3\{k4\},ymm2,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d ac 53 dc[ 	]*vpdpwssds ymm3\{k4\}\{z\},ymm2,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2d 53 9c f4 c0 1d fe ff[ 	]*vpdpwssds ymm3\{k5\},ymm2,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2d 53 5a 7f[ 	]*vpdpwssds ymm3\{k5\},ymm2,YMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 3d 53 5a 7f[ 	]*vpdpwssds ymm3\{k5\},ymm2,DWORD PTR \[edx\+0x1fc\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 0f 50 dc[ 	]*vpdpbusd xmm3\{k7\},xmm4,xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 8f 50 dc[ 	]*vpdpbusd xmm3\{k7\}\{z\},xmm4,xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 09 50 9c f4 c0 1d fe ff[ 	]*vpdpbusd xmm3\{k1\},xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 09 50 5a 7f[ 	]*vpdpbusd xmm3\{k1\},xmm4,XMMWORD PTR \[edx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 19 50 5a 7f[ 	]*vpdpbusd xmm3\{k1\},xmm4,DWORD PTR \[edx\+0x1fc\]\{1to4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2d 50 f4[ 	]*vpdpbusd ymm6\{k5\},ymm2,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d ad 50 f4[ 	]*vpdpbusd ymm6\{k5\}\{z\},ymm2,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2d 50 b4 f4 c0 1d fe ff[ 	]*vpdpbusd ymm6\{k5\},ymm2,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2d 50 72 7f[ 	]*vpdpbusd ymm6\{k5\},ymm2,YMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 3d 50 72 7f[ 	]*vpdpbusd ymm6\{k5\},ymm2,DWORD PTR \[edx\+0x1fc\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 0d 51 dc[ 	]*vpdpbusds xmm3\{k5\},xmm3,xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 8d 51 dc[ 	]*vpdpbusds xmm3\{k5\}\{z\},xmm3,xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 0c 51 9c f4 c0 1d fe ff[ 	]*vpdpbusds xmm3\{k4\},xmm3,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 0c 51 5a 7f[ 	]*vpdpbusds xmm3\{k4\},xmm3,XMMWORD PTR \[edx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 1c 51 5a 7f[ 	]*vpdpbusds xmm3\{k4\},xmm3,DWORD PTR \[edx\+0x1fc\]\{1to4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 2c 51 d4[ 	]*vpdpbusds ymm2\{k4\},ymm3,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 ac 51 d4[ 	]*vpdpbusds ymm2\{k4\}\{z\},ymm3,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 29 51 94 f4 c0 1d fe ff[ 	]*vpdpbusds ymm2\{k1\},ymm3,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 29 51 52 7f[ 	]*vpdpbusds ymm2\{k1\},ymm3,YMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 39 51 52 7f[ 	]*vpdpbusds ymm2\{k1\},ymm3,DWORD PTR \[edx\+0x1fc\]\{1to8\}
+#pass
diff --git a/gas/testsuite/gas/i386/avx512vnni_vl.d b/gas/testsuite/gas/i386/avx512vnni_vl.d
new file mode 100644
index 0000000000..f4a096ebd8
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vnni_vl.d
@@ -0,0 +1,92 @@
+#as:
+#objdump: -dw
+#name: i386 AVX512VNNI/VL insns
+#source: avx512vnni_vl.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 0b 52 d2[ 	]*vpdpwssd %xmm2,%xmm4,%xmm2\{%k3\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 8b 52 d2[ 	]*vpdpwssd %xmm2,%xmm4,%xmm2\{%k3\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 09 52 94 f4 c0 1d fe ff[ 	]*vpdpwssd -0x1e240\(%esp,%esi,8\),%xmm4,%xmm2\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 09 52 52 7f[ 	]*vpdpwssd 0x7f0\(%edx\),%xmm4,%xmm2\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 19 52 52 7f[ 	]*vpdpwssd 0x1fc\(%edx\)\{1to4\},%xmm4,%xmm2\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 29 52 d9[ 	]*vpdpwssd %ymm1,%ymm3,%ymm3\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 a9 52 d9[ 	]*vpdpwssd %ymm1,%ymm3,%ymm3\{%k1\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 2c 52 9c f4 c0 1d fe ff[ 	]*vpdpwssd -0x1e240\(%esp,%esi,8\),%ymm3,%ymm3\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 2c 52 5a 7f[ 	]*vpdpwssd 0xfe0\(%edx\),%ymm3,%ymm3\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 3c 52 5a 7f[ 	]*vpdpwssd 0x1fc\(%edx\)\{1to8\},%ymm3,%ymm3\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 09 53 d1[ 	]*vpdpwssds %xmm1,%xmm4,%xmm2\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 89 53 d1[ 	]*vpdpwssds %xmm1,%xmm4,%xmm2\{%k1\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 0c 53 94 f4 c0 1d fe ff[ 	]*vpdpwssds -0x1e240\(%esp,%esi,8\),%xmm4,%xmm2\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 0c 53 52 7f[ 	]*vpdpwssds 0x7f0\(%edx\),%xmm4,%xmm2\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 1c 53 52 7f[ 	]*vpdpwssds 0x1fc\(%edx\)\{1to4\},%xmm4,%xmm2\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 2f 53 e4[ 	]*vpdpwssds %ymm4,%ymm1,%ymm4\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 af 53 e4[ 	]*vpdpwssds %ymm4,%ymm1,%ymm4\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 2b 53 a4 f4 c0 1d fe ff[ 	]*vpdpwssds -0x1e240\(%esp,%esi,8\),%ymm1,%ymm4\{%k3\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 2b 53 62 7f[ 	]*vpdpwssds 0xfe0\(%edx\),%ymm1,%ymm4\{%k3\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 3b 53 62 7f[ 	]*vpdpwssds 0x1fc\(%edx\)\{1to8\},%ymm1,%ymm4\{%k3\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 0c 50 d1[ 	]*vpdpbusd %xmm1,%xmm3,%xmm2\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 8c 50 d1[ 	]*vpdpbusd %xmm1,%xmm3,%xmm2\{%k4\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 0a 50 94 f4 c0 1d fe ff[ 	]*vpdpbusd -0x1e240\(%esp,%esi,8\),%xmm3,%xmm2\{%k2\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 0a 50 52 7f[ 	]*vpdpbusd 0x7f0\(%edx\),%xmm3,%xmm2\{%k2\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 1a 50 52 7f[ 	]*vpdpbusd 0x1fc\(%edx\)\{1to4\},%xmm3,%xmm2\{%k2\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2d 50 d2[ 	]*vpdpbusd %ymm2,%ymm2,%ymm2\{%k5\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d ad 50 d2[ 	]*vpdpbusd %ymm2,%ymm2,%ymm2\{%k5\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2f 50 94 f4 c0 1d fe ff[ 	]*vpdpbusd -0x1e240\(%esp,%esi,8\),%ymm2,%ymm2\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2f 50 52 7f[ 	]*vpdpbusd 0xfe0\(%edx\),%ymm2,%ymm2\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 3f 50 52 7f[ 	]*vpdpbusd 0x1fc\(%edx\)\{1to8\},%ymm2,%ymm2\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 0e 51 f4[ 	]*vpdpbusds %xmm4,%xmm2,%xmm6\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 8e 51 f4[ 	]*vpdpbusds %xmm4,%xmm2,%xmm6\{%k6\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 0c 51 b4 f4 c0 1d fe ff[ 	]*vpdpbusds -0x1e240\(%esp,%esi,8\),%xmm2,%xmm6\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 0c 51 72 7f[ 	]*vpdpbusds 0x7f0\(%edx\),%xmm2,%xmm6\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 1c 51 72 7f[ 	]*vpdpbusds 0x1fc\(%edx\)\{1to4\},%xmm2,%xmm6\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 2f 51 e1[ 	]*vpdpbusds %ymm1,%ymm3,%ymm4\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 af 51 e1[ 	]*vpdpbusds %ymm1,%ymm3,%ymm4\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 29 51 a4 f4 c0 1d fe ff[ 	]*vpdpbusds -0x1e240\(%esp,%esi,8\),%ymm3,%ymm4\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 29 51 62 7f[ 	]*vpdpbusds 0xfe0\(%edx\),%ymm3,%ymm4\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 39 51 62 7f[ 	]*vpdpbusds 0x1fc\(%edx\)\{1to8\},%ymm3,%ymm4\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 09 52 ea[ 	]*vpdpwssd %xmm2,%xmm2,%xmm5\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 89 52 ea[ 	]*vpdpwssd %xmm2,%xmm2,%xmm5\{%k1\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 0e 52 ac f4 c0 1d fe ff[ 	]*vpdpwssd -0x1e240\(%esp,%esi,8\),%xmm2,%xmm5\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 0e 52 6a 7f[ 	]*vpdpwssd 0x7f0\(%edx\),%xmm2,%xmm5\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 1e 52 6a 7f[ 	]*vpdpwssd 0x1fc\(%edx\)\{1to4\},%xmm2,%xmm5\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2f 52 cc[ 	]*vpdpwssd %ymm4,%ymm2,%ymm1\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d af 52 cc[ 	]*vpdpwssd %ymm4,%ymm2,%ymm1\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2e 52 8c f4 c0 1d fe ff[ 	]*vpdpwssd -0x1e240\(%esp,%esi,8\),%ymm2,%ymm1\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2e 52 4a 7f[ 	]*vpdpwssd 0xfe0\(%edx\),%ymm2,%ymm1\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 3e 52 4a 7f[ 	]*vpdpwssd 0x1fc\(%edx\)\{1to8\},%ymm2,%ymm1\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 0a 53 c9[ 	]*vpdpwssds %xmm1,%xmm4,%xmm1\{%k2\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 8a 53 c9[ 	]*vpdpwssds %xmm1,%xmm4,%xmm1\{%k2\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 0e 53 8c f4 c0 1d fe ff[ 	]*vpdpwssds -0x1e240\(%esp,%esi,8\),%xmm4,%xmm1\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 0e 53 4a 7f[ 	]*vpdpwssds 0x7f0\(%edx\),%xmm4,%xmm1\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 1e 53 4a 7f[ 	]*vpdpwssds 0x1fc\(%edx\)\{1to4\},%xmm4,%xmm1\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2c 53 dc[ 	]*vpdpwssds %ymm4,%ymm2,%ymm3\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d ac 53 dc[ 	]*vpdpwssds %ymm4,%ymm2,%ymm3\{%k4\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2d 53 9c f4 c0 1d fe ff[ 	]*vpdpwssds -0x1e240\(%esp,%esi,8\),%ymm2,%ymm3\{%k5\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2d 53 5a 7f[ 	]*vpdpwssds 0xfe0\(%edx\),%ymm2,%ymm3\{%k5\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 3d 53 5a 7f[ 	]*vpdpwssds 0x1fc\(%edx\)\{1to8\},%ymm2,%ymm3\{%k5\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 0f 50 dc[ 	]*vpdpbusd %xmm4,%xmm4,%xmm3\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 8f 50 dc[ 	]*vpdpbusd %xmm4,%xmm4,%xmm3\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 09 50 9c f4 c0 1d fe ff[ 	]*vpdpbusd -0x1e240\(%esp,%esi,8\),%xmm4,%xmm3\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 09 50 5a 7f[ 	]*vpdpbusd 0x7f0\(%edx\),%xmm4,%xmm3\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 5d 19 50 5a 7f[ 	]*vpdpbusd 0x1fc\(%edx\)\{1to4\},%xmm4,%xmm3\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2d 50 f4[ 	]*vpdpbusd %ymm4,%ymm2,%ymm6\{%k5\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d ad 50 f4[ 	]*vpdpbusd %ymm4,%ymm2,%ymm6\{%k5\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2d 50 b4 f4 c0 1d fe ff[ 	]*vpdpbusd -0x1e240\(%esp,%esi,8\),%ymm2,%ymm6\{%k5\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 2d 50 72 7f[ 	]*vpdpbusd 0xfe0\(%edx\),%ymm2,%ymm6\{%k5\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 6d 3d 50 72 7f[ 	]*vpdpbusd 0x1fc\(%edx\)\{1to8\},%ymm2,%ymm6\{%k5\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 0d 51 dc[ 	]*vpdpbusds %xmm4,%xmm3,%xmm3\{%k5\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 8d 51 dc[ 	]*vpdpbusds %xmm4,%xmm3,%xmm3\{%k5\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 0c 51 9c f4 c0 1d fe ff[ 	]*vpdpbusds -0x1e240\(%esp,%esi,8\),%xmm3,%xmm3\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 0c 51 5a 7f[ 	]*vpdpbusds 0x7f0\(%edx\),%xmm3,%xmm3\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 1c 51 5a 7f[ 	]*vpdpbusds 0x1fc\(%edx\)\{1to4\},%xmm3,%xmm3\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 2c 51 d4[ 	]*vpdpbusds %ymm4,%ymm3,%ymm2\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 ac 51 d4[ 	]*vpdpbusds %ymm4,%ymm3,%ymm2\{%k4\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 29 51 94 f4 c0 1d fe ff[ 	]*vpdpbusds -0x1e240\(%esp,%esi,8\),%ymm3,%ymm2\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 29 51 52 7f[ 	]*vpdpbusds 0xfe0\(%edx\),%ymm3,%ymm2\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 65 39 51 52 7f[ 	]*vpdpbusds 0x1fc\(%edx\)\{1to8\},%ymm3,%ymm2\{%k1\}
+#pass
diff --git a/gas/testsuite/gas/i386/avx512vnni_vl.s b/gas/testsuite/gas/i386/avx512vnni_vl.s
new file mode 100644
index 0000000000..f61e179fae
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vnni_vl.s
@@ -0,0 +1,93 @@
+# Check 32bit AVX512{VNNI,VL} instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vpdpwssd	%xmm2, %xmm4, %xmm2{%k3}	 # AVX512{VNNI,VL}
+	vpdpwssd	%xmm2, %xmm4, %xmm2{%k3}{z}	 # AVX512{VNNI,VL}
+	vpdpwssd	-123456(%esp,%esi,8), %xmm4, %xmm2{%k1}	 # AVX512{VNNI,VL}
+	vpdpwssd	2032(%edx), %xmm4, %xmm2{%k1}	 # AVX512{VNNI,VL} Disp8
+	vpdpwssd	508(%edx){1to4}, %xmm4, %xmm2{%k1}	 # AVX512{VNNI,VL} Disp8
+	vpdpwssd	%ymm1, %ymm3, %ymm3{%k1}	 # AVX512{VNNI,VL}
+	vpdpwssd	%ymm1, %ymm3, %ymm3{%k1}{z}	 # AVX512{VNNI,VL}
+	vpdpwssd	-123456(%esp,%esi,8), %ymm3, %ymm3{%k4}	 # AVX512{VNNI,VL}
+	vpdpwssd	4064(%edx), %ymm3, %ymm3{%k4}	 # AVX512{VNNI,VL} Disp8
+	vpdpwssd	508(%edx){1to8}, %ymm3, %ymm3{%k4}	 # AVX512{VNNI,VL} Disp8
+
+	vpdpwssds	%xmm1, %xmm4, %xmm2{%k1}	 # AVX512{VNNI,VL}
+	vpdpwssds	%xmm1, %xmm4, %xmm2{%k1}{z}	 # AVX512{VNNI,VL}
+	vpdpwssds	-123456(%esp,%esi,8), %xmm4, %xmm2{%k4}	 # AVX512{VNNI,VL}
+	vpdpwssds	2032(%edx), %xmm4, %xmm2{%k4}	 # AVX512{VNNI,VL} Disp8
+	vpdpwssds	508(%edx){1to4}, %xmm4, %xmm2{%k4}	 # AVX512{VNNI,VL} Disp8
+	vpdpwssds	%ymm4, %ymm1, %ymm4{%k7}	 # AVX512{VNNI,VL}
+	vpdpwssds	%ymm4, %ymm1, %ymm4{%k7}{z}	 # AVX512{VNNI,VL}
+	vpdpwssds	-123456(%esp,%esi,8), %ymm1, %ymm4{%k3}	 # AVX512{VNNI,VL}
+	vpdpwssds	4064(%edx), %ymm1, %ymm4{%k3}	 # AVX512{VNNI,VL} Disp8
+	vpdpwssds	508(%edx){1to8}, %ymm1, %ymm4{%k3}	 # AVX512{VNNI,VL} Disp8
+
+	vpdpbusd	%xmm1, %xmm3, %xmm2{%k4}	 # AVX512{VNNI,VL}
+	vpdpbusd	%xmm1, %xmm3, %xmm2{%k4}{z}	 # AVX512{VNNI,VL}
+	vpdpbusd	-123456(%esp,%esi,8), %xmm3, %xmm2{%k2}	 # AVX512{VNNI,VL}
+	vpdpbusd	2032(%edx), %xmm3, %xmm2{%k2}	 # AVX512{VNNI,VL} Disp8
+	vpdpbusd	508(%edx){1to4}, %xmm3, %xmm2{%k2}	 # AVX512{VNNI,VL} Disp8
+	vpdpbusd	%ymm2, %ymm2, %ymm2{%k5}	 # AVX512{VNNI,VL}
+	vpdpbusd	%ymm2, %ymm2, %ymm2{%k5}{z}	 # AVX512{VNNI,VL}
+	vpdpbusd	-123456(%esp,%esi,8), %ymm2, %ymm2{%k7}	 # AVX512{VNNI,VL}
+	vpdpbusd	4064(%edx), %ymm2, %ymm2{%k7}	 # AVX512{VNNI,VL} Disp8
+	vpdpbusd	508(%edx){1to8}, %ymm2, %ymm2{%k7}	 # AVX512{VNNI,VL} Disp8
+
+	vpdpbusds	%xmm4, %xmm2, %xmm6{%k6}	 # AVX512{VNNI,VL}
+	vpdpbusds	%xmm4, %xmm2, %xmm6{%k6}{z}	 # AVX512{VNNI,VL}
+	vpdpbusds	-123456(%esp,%esi,8), %xmm2, %xmm6{%k4}	 # AVX512{VNNI,VL}
+	vpdpbusds	2032(%edx), %xmm2, %xmm6{%k4}	 # AVX512{VNNI,VL} Disp8
+	vpdpbusds	508(%edx){1to4}, %xmm2, %xmm6{%k4}	 # AVX512{VNNI,VL} Disp8
+	vpdpbusds	%ymm1, %ymm3, %ymm4{%k7}	 # AVX512{VNNI,VL}
+	vpdpbusds	%ymm1, %ymm3, %ymm4{%k7}{z}	 # AVX512{VNNI,VL}
+	vpdpbusds	-123456(%esp,%esi,8), %ymm3, %ymm4{%k1}	 # AVX512{VNNI,VL}
+	vpdpbusds	4064(%edx), %ymm3, %ymm4{%k1}	 # AVX512{VNNI,VL} Disp8
+	vpdpbusds	508(%edx){1to8}, %ymm3, %ymm4{%k1}	 # AVX512{VNNI,VL} Disp8
+
+	.intel_syntax noprefix
+	vpdpwssd	xmm5{k1}, xmm2, xmm2	 # AVX512{VNNI,VL}
+	vpdpwssd	xmm5{k1}{z}, xmm2, xmm2	 # AVX512{VNNI,VL}
+	vpdpwssd	xmm5{k6}, xmm2, XMMWORD PTR [esp+esi*8-123456]	 # AVX512{VNNI,VL}
+	vpdpwssd	xmm5{k6}, xmm2, XMMWORD PTR [edx+2032]	 # AVX512{VNNI,VL} Disp8
+	vpdpwssd	xmm5{k6}, xmm2, [edx+508]{1to4}	 # AVX512{VNNI,VL} Disp8
+	vpdpwssd	ymm1{k7}, ymm2, ymm4	 # AVX512{VNNI,VL}
+	vpdpwssd	ymm1{k7}{z}, ymm2, ymm4	 # AVX512{VNNI,VL}
+	vpdpwssd	ymm1{k6}, ymm2, YMMWORD PTR [esp+esi*8-123456]	 # AVX512{VNNI,VL}
+	vpdpwssd	ymm1{k6}, ymm2, YMMWORD PTR [edx+4064]	 # AVX512{VNNI,VL} Disp8
+	vpdpwssd	ymm1{k6}, ymm2, [edx+508]{1to8}	 # AVX512{VNNI,VL} Disp8
+
+	vpdpwssds	xmm1{k2}, xmm4, xmm1	 # AVX512{VNNI,VL}
+	vpdpwssds	xmm1{k2}{z}, xmm4, xmm1	 # AVX512{VNNI,VL}
+	vpdpwssds	xmm1{k6}, xmm4, XMMWORD PTR [esp+esi*8-123456]	 # AVX512{VNNI,VL}
+	vpdpwssds	xmm1{k6}, xmm4, XMMWORD PTR [edx+2032]	 # AVX512{VNNI,VL} Disp8
+	vpdpwssds	xmm1{k6}, xmm4, [edx+508]{1to4}	 # AVX512{VNNI,VL} Disp8
+	vpdpwssds	ymm3{k4}, ymm2, ymm4	 # AVX512{VNNI,VL}
+	vpdpwssds	ymm3{k4}{z}, ymm2, ymm4	 # AVX512{VNNI,VL}
+	vpdpwssds	ymm3{k5}, ymm2, YMMWORD PTR [esp+esi*8-123456]	 # AVX512{VNNI,VL}
+	vpdpwssds	ymm3{k5}, ymm2, YMMWORD PTR [edx+4064]	 # AVX512{VNNI,VL} Disp8
+	vpdpwssds	ymm3{k5}, ymm2, [edx+508]{1to8}	 # AVX512{VNNI,VL} Disp8
+
+	vpdpbusd	xmm3{k7}, xmm4, xmm4	 # AVX512{VNNI,VL}
+	vpdpbusd	xmm3{k7}{z}, xmm4, xmm4	 # AVX512{VNNI,VL}
+	vpdpbusd	xmm3{k1}, xmm4, XMMWORD PTR [esp+esi*8-123456]	 # AVX512{VNNI,VL}
+	vpdpbusd	xmm3{k1}, xmm4, XMMWORD PTR [edx+2032]	 # AVX512{VNNI,VL} Disp8
+	vpdpbusd	xmm3{k1}, xmm4, [edx+508]{1to4}	 # AVX512{VNNI,VL} Disp8
+	vpdpbusd	ymm6{k5}, ymm2, ymm4	 # AVX512{VNNI,VL}
+	vpdpbusd	ymm6{k5}{z}, ymm2, ymm4	 # AVX512{VNNI,VL}
+	vpdpbusd	ymm6{k5}, ymm2, YMMWORD PTR [esp+esi*8-123456]	 # AVX512{VNNI,VL}
+	vpdpbusd	ymm6{k5}, ymm2, YMMWORD PTR [edx+4064]	 # AVX512{VNNI,VL} Disp8
+	vpdpbusd	ymm6{k5}, ymm2, [edx+508]{1to8}	 # AVX512{VNNI,VL} Disp8
+
+	vpdpbusds	xmm3{k5}, xmm3, xmm4	 # AVX512{VNNI,VL}
+	vpdpbusds	xmm3{k5}{z}, xmm3, xmm4	 # AVX512{VNNI,VL}
+	vpdpbusds	xmm3{k4}, xmm3, XMMWORD PTR [esp+esi*8-123456]	 # AVX512{VNNI,VL}
+	vpdpbusds	xmm3{k4}, xmm3, XMMWORD PTR [edx+2032]	 # AVX512{VNNI,VL} Disp8
+	vpdpbusds	xmm3{k4}, xmm3, [edx+508]{1to4}	 # AVX512{VNNI,VL} Disp8
+	vpdpbusds	ymm2{k4}, ymm3, ymm4	 # AVX512{VNNI,VL}
+	vpdpbusds	ymm2{k4}{z}, ymm3, ymm4	 # AVX512{VNNI,VL}
+	vpdpbusds	ymm2{k1}, ymm3, YMMWORD PTR [esp+esi*8-123456]	 # AVX512{VNNI,VL}
+	vpdpbusds	ymm2{k1}, ymm3, YMMWORD PTR [edx+4064]	 # AVX512{VNNI,VL} Disp8
+	vpdpbusds	ymm2{k1}, ymm3, [edx+508]{1to8}	 # AVX512{VNNI,VL} Disp8
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 78c35625e7..0c79bbf113 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -394,6 +394,10 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "avx512vl_vpclmulqdq-intel"
     run_dump_test "avx512vl_vpclmulqdq-wig1"
     run_dump_test "avx512vl_vpclmulqdq-wig1-intel"
+    run_dump_test "avx512vnni"
+    run_dump_test "avx512vnni-intel"
+    run_dump_test "avx512vnni_vl"
+    run_dump_test "avx512vnni_vl-intel"
     run_dump_test "clzero"
     run_dump_test "disassem"
     run_dump_test "mwaitx-bdver4"
@@ -847,6 +851,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-avx512vl_vpclmulqdq-intel"
     run_dump_test "x86-64-avx512vl_vpclmulqdq-wig1"
     run_dump_test "x86-64-avx512vl_vpclmulqdq-wig1-intel"
+    run_dump_test "x86-64-avx512vnni"
+    run_dump_test "x86-64-avx512vnni-intel"
+    run_dump_test "x86-64-avx512vnni_vl"
+    run_dump_test "x86-64-avx512vnni_vl-intel"
     run_dump_test "x86-64-clzero"
     run_dump_test "x86-64-mwaitx-bdver4"
     run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/x86-64-avx512vnni-intel.d b/gas/testsuite/gas/i386/x86-64-avx512vnni-intel.d
new file mode 100644
index 0000000000..2a721e7966
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512vnni-intel.d
@@ -0,0 +1,60 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 AVX512VNNI insns (Intel disassembly)
+#source: x86-64-avx512vnni.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d 40 52 d1[ 	]*vpdpwssd zmm18,zmm18,zmm17
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d 45 52 d1[ 	]*vpdpwssd zmm18\{k5\},zmm18,zmm17
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d c5 52 d1[ 	]*vpdpwssd zmm18\{k5\}\{z\},zmm18,zmm17
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d 40 52 94 f0 23 01 00 00[ 	]*vpdpwssd zmm18,zmm18,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 6d 40 52 52 7f[ 	]*vpdpwssd zmm18,zmm18,ZMMWORD PTR \[rdx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 6d 50 52 52 7f[ 	]*vpdpwssd zmm18,zmm18,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 55 40 53 e9[ 	]*vpdpwssds zmm21,zmm21,zmm17
+[ 	]*[a-f0-9]+:[ 	]*62 a2 55 44 53 e9[ 	]*vpdpwssds zmm21\{k4\},zmm21,zmm17
+[ 	]*[a-f0-9]+:[ 	]*62 a2 55 c4 53 e9[ 	]*vpdpwssds zmm21\{k4\}\{z\},zmm21,zmm17
+[ 	]*[a-f0-9]+:[ 	]*62 a2 55 40 53 ac f0 23 01 00 00[ 	]*vpdpwssds zmm21,zmm21,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 55 40 53 6a 7f[ 	]*vpdpwssds zmm21,zmm21,ZMMWORD PTR \[rdx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 55 50 53 6a 7f[ 	]*vpdpwssds zmm21,zmm21,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 55 40 50 fa[ 	]*vpdpbusd zmm23,zmm21,zmm18
+[ 	]*[a-f0-9]+:[ 	]*62 a2 55 44 50 fa[ 	]*vpdpbusd zmm23\{k4\},zmm21,zmm18
+[ 	]*[a-f0-9]+:[ 	]*62 a2 55 c4 50 fa[ 	]*vpdpbusd zmm23\{k4\}\{z\},zmm21,zmm18
+[ 	]*[a-f0-9]+:[ 	]*62 a2 55 40 50 bc f0 23 01 00 00[ 	]*vpdpbusd zmm23,zmm21,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 55 40 50 7a 7f[ 	]*vpdpbusd zmm23,zmm21,ZMMWORD PTR \[rdx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 55 50 50 7a 7f[ 	]*vpdpbusd zmm23,zmm21,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 3d 40 51 c1[ 	]*vpdpbusds zmm24,zmm24,zmm25
+[ 	]*[a-f0-9]+:[ 	]*62 02 3d 47 51 c1[ 	]*vpdpbusds zmm24\{k7\},zmm24,zmm25
+[ 	]*[a-f0-9]+:[ 	]*62 02 3d c7 51 c1[ 	]*vpdpbusds zmm24\{k7\}\{z\},zmm24,zmm25
+[ 	]*[a-f0-9]+:[ 	]*62 22 3d 40 51 84 f0 23 01 00 00[ 	]*vpdpbusds zmm24,zmm24,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 3d 40 51 42 7f[ 	]*vpdpbusds zmm24,zmm24,ZMMWORD PTR \[rdx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 3d 50 51 42 7f[ 	]*vpdpbusds zmm24,zmm24,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 40 52 e1[ 	]*vpdpwssd zmm28,zmm27,zmm17
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 47 52 e1[ 	]*vpdpwssd zmm28\{k7\},zmm27,zmm17
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 c7 52 e1[ 	]*vpdpwssd zmm28\{k7\}\{z\},zmm27,zmm17
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 40 52 a4 f0 34 12 00 00[ 	]*vpdpwssd zmm28,zmm27,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 25 40 52 62 7f[ 	]*vpdpwssd zmm28,zmm27,ZMMWORD PTR \[rdx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 25 50 52 62 7f[ 	]*vpdpwssd zmm28,zmm27,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 1d 40 53 e9[ 	]*vpdpwssds zmm29,zmm28,zmm17
+[ 	]*[a-f0-9]+:[ 	]*62 22 1d 43 53 e9[ 	]*vpdpwssds zmm29\{k3\},zmm28,zmm17
+[ 	]*[a-f0-9]+:[ 	]*62 22 1d c3 53 e9[ 	]*vpdpwssds zmm29\{k3\}\{z\},zmm28,zmm17
+[ 	]*[a-f0-9]+:[ 	]*62 22 1d 40 53 ac f0 34 12 00 00[ 	]*vpdpwssds zmm29,zmm28,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 1d 40 53 6a 7f[ 	]*vpdpwssds zmm29,zmm28,ZMMWORD PTR \[rdx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 1d 50 53 6a 7f[ 	]*vpdpwssds zmm29,zmm28,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 3d 40 50 e5[ 	]*vpdpbusd zmm28,zmm24,zmm21
+[ 	]*[a-f0-9]+:[ 	]*62 22 3d 46 50 e5[ 	]*vpdpbusd zmm28\{k6\},zmm24,zmm21
+[ 	]*[a-f0-9]+:[ 	]*62 22 3d c6 50 e5[ 	]*vpdpbusd zmm28\{k6\}\{z\},zmm24,zmm21
+[ 	]*[a-f0-9]+:[ 	]*62 22 3d 40 50 a4 f0 34 12 00 00[ 	]*vpdpbusd zmm28,zmm24,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 3d 40 50 62 7f[ 	]*vpdpbusd zmm28,zmm24,ZMMWORD PTR \[rdx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 3d 50 50 62 7f[ 	]*vpdpbusd zmm28,zmm24,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 75 40 51 e4[ 	]*vpdpbusds zmm20,zmm17,zmm20
+[ 	]*[a-f0-9]+:[ 	]*62 a2 75 42 51 e4[ 	]*vpdpbusds zmm20\{k2\},zmm17,zmm20
+[ 	]*[a-f0-9]+:[ 	]*62 a2 75 c2 51 e4[ 	]*vpdpbusds zmm20\{k2\}\{z\},zmm17,zmm20
+[ 	]*[a-f0-9]+:[ 	]*62 a2 75 40 51 a4 f0 34 12 00 00[ 	]*vpdpbusds zmm20,zmm17,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 75 40 51 62 7f[ 	]*vpdpbusds zmm20,zmm17,ZMMWORD PTR \[rdx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 75 50 51 62 7f[ 	]*vpdpbusds zmm20,zmm17,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512vnni.d b/gas/testsuite/gas/i386/x86-64-avx512vnni.d
new file mode 100644
index 0000000000..bd164bf3a8
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512vnni.d
@@ -0,0 +1,60 @@
+#as:
+#objdump: -dw
+#name: x86_64 AVX512VNNI insns
+#source: x86-64-avx512vnni.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d 40 52 d1[ 	]*vpdpwssd %zmm17,%zmm18,%zmm18
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d 45 52 d1[ 	]*vpdpwssd %zmm17,%zmm18,%zmm18\{%k5\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d c5 52 d1[ 	]*vpdpwssd %zmm17,%zmm18,%zmm18\{%k5\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d 40 52 94 f0 23 01 00 00[ 	]*vpdpwssd 0x123\(%rax,%r14,8\),%zmm18,%zmm18
+[ 	]*[a-f0-9]+:[ 	]*62 e2 6d 40 52 52 7f[ 	]*vpdpwssd 0x1fc0\(%rdx\),%zmm18,%zmm18
+[ 	]*[a-f0-9]+:[ 	]*62 e2 6d 50 52 52 7f[ 	]*vpdpwssd 0x1fc\(%rdx\)\{1to16\},%zmm18,%zmm18
+[ 	]*[a-f0-9]+:[ 	]*62 a2 55 40 53 e9[ 	]*vpdpwssds %zmm17,%zmm21,%zmm21
+[ 	]*[a-f0-9]+:[ 	]*62 a2 55 44 53 e9[ 	]*vpdpwssds %zmm17,%zmm21,%zmm21\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 55 c4 53 e9[ 	]*vpdpwssds %zmm17,%zmm21,%zmm21\{%k4\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 55 40 53 ac f0 23 01 00 00[ 	]*vpdpwssds 0x123\(%rax,%r14,8\),%zmm21,%zmm21
+[ 	]*[a-f0-9]+:[ 	]*62 e2 55 40 53 6a 7f[ 	]*vpdpwssds 0x1fc0\(%rdx\),%zmm21,%zmm21
+[ 	]*[a-f0-9]+:[ 	]*62 e2 55 50 53 6a 7f[ 	]*vpdpwssds 0x1fc\(%rdx\)\{1to16\},%zmm21,%zmm21
+[ 	]*[a-f0-9]+:[ 	]*62 a2 55 40 50 fa[ 	]*vpdpbusd %zmm18,%zmm21,%zmm23
+[ 	]*[a-f0-9]+:[ 	]*62 a2 55 44 50 fa[ 	]*vpdpbusd %zmm18,%zmm21,%zmm23\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 55 c4 50 fa[ 	]*vpdpbusd %zmm18,%zmm21,%zmm23\{%k4\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 55 40 50 bc f0 23 01 00 00[ 	]*vpdpbusd 0x123\(%rax,%r14,8\),%zmm21,%zmm23
+[ 	]*[a-f0-9]+:[ 	]*62 e2 55 40 50 7a 7f[ 	]*vpdpbusd 0x1fc0\(%rdx\),%zmm21,%zmm23
+[ 	]*[a-f0-9]+:[ 	]*62 e2 55 50 50 7a 7f[ 	]*vpdpbusd 0x1fc\(%rdx\)\{1to16\},%zmm21,%zmm23
+[ 	]*[a-f0-9]+:[ 	]*62 02 3d 40 51 c1[ 	]*vpdpbusds %zmm25,%zmm24,%zmm24
+[ 	]*[a-f0-9]+:[ 	]*62 02 3d 47 51 c1[ 	]*vpdpbusds %zmm25,%zmm24,%zmm24\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 3d c7 51 c1[ 	]*vpdpbusds %zmm25,%zmm24,%zmm24\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 3d 40 51 84 f0 23 01 00 00[ 	]*vpdpbusds 0x123\(%rax,%r14,8\),%zmm24,%zmm24
+[ 	]*[a-f0-9]+:[ 	]*62 62 3d 40 51 42 7f[ 	]*vpdpbusds 0x1fc0\(%rdx\),%zmm24,%zmm24
+[ 	]*[a-f0-9]+:[ 	]*62 62 3d 50 51 42 7f[ 	]*vpdpbusds 0x1fc\(%rdx\)\{1to16\},%zmm24,%zmm24
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 40 52 e1[ 	]*vpdpwssd %zmm17,%zmm27,%zmm28
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 47 52 e1[ 	]*vpdpwssd %zmm17,%zmm27,%zmm28\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 c7 52 e1[ 	]*vpdpwssd %zmm17,%zmm27,%zmm28\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 40 52 a4 f0 34 12 00 00[ 	]*vpdpwssd 0x1234\(%rax,%r14,8\),%zmm27,%zmm28
+[ 	]*[a-f0-9]+:[ 	]*62 62 25 40 52 62 7f[ 	]*vpdpwssd 0x1fc0\(%rdx\),%zmm27,%zmm28
+[ 	]*[a-f0-9]+:[ 	]*62 62 25 50 52 62 7f[ 	]*vpdpwssd 0x1fc\(%rdx\)\{1to16\},%zmm27,%zmm28
+[ 	]*[a-f0-9]+:[ 	]*62 22 1d 40 53 e9[ 	]*vpdpwssds %zmm17,%zmm28,%zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 22 1d 43 53 e9[ 	]*vpdpwssds %zmm17,%zmm28,%zmm29\{%k3\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 1d c3 53 e9[ 	]*vpdpwssds %zmm17,%zmm28,%zmm29\{%k3\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 1d 40 53 ac f0 34 12 00 00[ 	]*vpdpwssds 0x1234\(%rax,%r14,8\),%zmm28,%zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 62 1d 40 53 6a 7f[ 	]*vpdpwssds 0x1fc0\(%rdx\),%zmm28,%zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 62 1d 50 53 6a 7f[ 	]*vpdpwssds 0x1fc\(%rdx\)\{1to16\},%zmm28,%zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 22 3d 40 50 e5[ 	]*vpdpbusd %zmm21,%zmm24,%zmm28
+[ 	]*[a-f0-9]+:[ 	]*62 22 3d 46 50 e5[ 	]*vpdpbusd %zmm21,%zmm24,%zmm28\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 3d c6 50 e5[ 	]*vpdpbusd %zmm21,%zmm24,%zmm28\{%k6\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 3d 40 50 a4 f0 34 12 00 00[ 	]*vpdpbusd 0x1234\(%rax,%r14,8\),%zmm24,%zmm28
+[ 	]*[a-f0-9]+:[ 	]*62 62 3d 40 50 62 7f[ 	]*vpdpbusd 0x1fc0\(%rdx\),%zmm24,%zmm28
+[ 	]*[a-f0-9]+:[ 	]*62 62 3d 50 50 62 7f[ 	]*vpdpbusd 0x1fc\(%rdx\)\{1to16\},%zmm24,%zmm28
+[ 	]*[a-f0-9]+:[ 	]*62 a2 75 40 51 e4[ 	]*vpdpbusds %zmm20,%zmm17,%zmm20
+[ 	]*[a-f0-9]+:[ 	]*62 a2 75 42 51 e4[ 	]*vpdpbusds %zmm20,%zmm17,%zmm20\{%k2\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 75 c2 51 e4[ 	]*vpdpbusds %zmm20,%zmm17,%zmm20\{%k2\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 75 40 51 a4 f0 34 12 00 00[ 	]*vpdpbusds 0x1234\(%rax,%r14,8\),%zmm17,%zmm20
+[ 	]*[a-f0-9]+:[ 	]*62 e2 75 40 51 62 7f[ 	]*vpdpbusds 0x1fc0\(%rdx\),%zmm17,%zmm20
+[ 	]*[a-f0-9]+:[ 	]*62 e2 75 50 51 62 7f[ 	]*vpdpbusds 0x1fc\(%rdx\)\{1to16\},%zmm17,%zmm20
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512vnni.s b/gas/testsuite/gas/i386/x86-64-avx512vnni.s
new file mode 100644
index 0000000000..8ae051c093
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512vnni.s
@@ -0,0 +1,61 @@
+# Check 64bit AVX512VNNI instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vpdpwssd	%zmm17, %zmm18, %zmm18	 # AVX512VNNI
+	vpdpwssd	%zmm17, %zmm18, %zmm18{%k5}	 # AVX512VNNI
+	vpdpwssd	%zmm17, %zmm18, %zmm18{%k5}{z}	 # AVX512VNNI
+	vpdpwssd	0x123(%rax,%r14,8), %zmm18, %zmm18	 # AVX512VNNI
+	vpdpwssd	8128(%rdx), %zmm18, %zmm18	 # AVX512VNNI Disp8
+	vpdpwssd	508(%rdx){1to16}, %zmm18, %zmm18	 # AVX512VNNI Disp8
+
+	vpdpwssds	%zmm17, %zmm21, %zmm21	 # AVX512VNNI
+	vpdpwssds	%zmm17, %zmm21, %zmm21{%k4}	 # AVX512VNNI
+	vpdpwssds	%zmm17, %zmm21, %zmm21{%k4}{z}	 # AVX512VNNI
+	vpdpwssds	0x123(%rax,%r14,8), %zmm21, %zmm21	 # AVX512VNNI
+	vpdpwssds	8128(%rdx), %zmm21, %zmm21	 # AVX512VNNI Disp8
+	vpdpwssds	508(%rdx){1to16}, %zmm21, %zmm21	 # AVX512VNNI Disp8
+
+	vpdpbusd	%zmm18, %zmm21, %zmm23	 # AVX512VNNI
+	vpdpbusd	%zmm18, %zmm21, %zmm23{%k4}	 # AVX512VNNI
+	vpdpbusd	%zmm18, %zmm21, %zmm23{%k4}{z}	 # AVX512VNNI
+	vpdpbusd	0x123(%rax,%r14,8), %zmm21, %zmm23	 # AVX512VNNI
+	vpdpbusd	8128(%rdx), %zmm21, %zmm23	 # AVX512VNNI Disp8
+	vpdpbusd	508(%rdx){1to16}, %zmm21, %zmm23	 # AVX512VNNI Disp8
+
+	vpdpbusds	%zmm25, %zmm24, %zmm24	 # AVX512VNNI
+	vpdpbusds	%zmm25, %zmm24, %zmm24{%k7}	 # AVX512VNNI
+	vpdpbusds	%zmm25, %zmm24, %zmm24{%k7}{z}	 # AVX512VNNI
+	vpdpbusds	0x123(%rax,%r14,8), %zmm24, %zmm24	 # AVX512VNNI
+	vpdpbusds	8128(%rdx), %zmm24, %zmm24	 # AVX512VNNI Disp8
+	vpdpbusds	508(%rdx){1to16}, %zmm24, %zmm24	 # AVX512VNNI Disp8
+
+	.intel_syntax noprefix
+	vpdpwssd	zmm28, zmm27, zmm17	 # AVX512VNNI
+	vpdpwssd	zmm28{k7}, zmm27, zmm17	 # AVX512VNNI
+	vpdpwssd	zmm28{k7}{z}, zmm27, zmm17	 # AVX512VNNI
+	vpdpwssd	zmm28, zmm27, ZMMWORD PTR [rax+r14*8+0x1234]	 # AVX512VNNI
+	vpdpwssd	zmm28, zmm27, ZMMWORD PTR [rdx+8128]	 # AVX512VNNI Disp8
+	vpdpwssd	zmm28, zmm27, [rdx+508]{1to16}	 # AVX512VNNI Disp8
+
+	vpdpwssds	zmm29, zmm28, zmm17	 # AVX512VNNI
+	vpdpwssds	zmm29{k3}, zmm28, zmm17	 # AVX512VNNI
+	vpdpwssds	zmm29{k3}{z}, zmm28, zmm17	 # AVX512VNNI
+	vpdpwssds	zmm29, zmm28, ZMMWORD PTR [rax+r14*8+0x1234]	 # AVX512VNNI
+	vpdpwssds	zmm29, zmm28, ZMMWORD PTR [rdx+8128]	 # AVX512VNNI Disp8
+	vpdpwssds	zmm29, zmm28, [rdx+508]{1to16}	 # AVX512VNNI Disp8
+
+	vpdpbusd	zmm28, zmm24, zmm21	 # AVX512VNNI
+	vpdpbusd	zmm28{k6}, zmm24, zmm21	 # AVX512VNNI
+	vpdpbusd	zmm28{k6}{z}, zmm24, zmm21	 # AVX512VNNI
+	vpdpbusd	zmm28, zmm24, ZMMWORD PTR [rax+r14*8+0x1234]	 # AVX512VNNI
+	vpdpbusd	zmm28, zmm24, ZMMWORD PTR [rdx+8128]	 # AVX512VNNI Disp8
+	vpdpbusd	zmm28, zmm24, [rdx+508]{1to16}	 # AVX512VNNI Disp8
+
+	vpdpbusds	zmm20, zmm17, zmm20	 # AVX512VNNI
+	vpdpbusds	zmm20{k2}, zmm17, zmm20	 # AVX512VNNI
+	vpdpbusds	zmm20{k2}{z}, zmm17, zmm20	 # AVX512VNNI
+	vpdpbusds	zmm20, zmm17, ZMMWORD PTR [rax+r14*8+0x1234]	 # AVX512VNNI
+	vpdpbusds	zmm20, zmm17, ZMMWORD PTR [rdx+8128]	 # AVX512VNNI Disp8
+	vpdpbusds	zmm20, zmm17, [rdx+508]{1to16}	 # AVX512VNNI Disp8
diff --git a/gas/testsuite/gas/i386/x86-64-avx512vnni_vl-intel.d b/gas/testsuite/gas/i386/x86-64-avx512vnni_vl-intel.d
new file mode 100644
index 0000000000..1e3fe98852
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512vnni_vl-intel.d
@@ -0,0 +1,108 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 AVX512VNNI/VL insns (Intel disassembly)
+#source: x86-64-avx512vnni_vl.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 22 4d 00 52 d4[ 	]*vpdpwssd xmm26,xmm22,xmm20
+[ 	]*[a-f0-9]+:[ 	]*62 22 4d 03 52 d4[ 	]*vpdpwssd xmm26\{k3\},xmm22,xmm20
+[ 	]*[a-f0-9]+:[ 	]*62 22 4d 83 52 d4[ 	]*vpdpwssd xmm26\{k3\}\{z\},xmm22,xmm20
+[ 	]*[a-f0-9]+:[ 	]*62 22 4d 00 52 94 f0 23 01 00 00[ 	]*vpdpwssd xmm26,xmm22,XMMWORD PTR \[rax\+r14\*8\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 4d 00 52 52 7f[ 	]*vpdpwssd xmm26,xmm22,XMMWORD PTR \[rdx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 4d 10 52 52 7f[ 	]*vpdpwssd xmm26,xmm22,DWORD PTR \[rdx\+0x1fc\]\{1to4\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 5d 20 52 e2[ 	]*vpdpwssd ymm20,ymm20,ymm18
+[ 	]*[a-f0-9]+:[ 	]*62 a2 5d 25 52 e2[ 	]*vpdpwssd ymm20\{k5\},ymm20,ymm18
+[ 	]*[a-f0-9]+:[ 	]*62 a2 5d a5 52 e2[ 	]*vpdpwssd ymm20\{k5\}\{z\},ymm20,ymm18
+[ 	]*[a-f0-9]+:[ 	]*62 a2 5d 20 52 a4 f0 23 01 00 00[ 	]*vpdpwssd ymm20,ymm20,YMMWORD PTR \[rax\+r14\*8\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 5d 20 52 62 7f[ 	]*vpdpwssd ymm20,ymm20,YMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 5d 30 52 62 7f[ 	]*vpdpwssd ymm20,ymm20,DWORD PTR \[rdx\+0x1fc\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 65 00 53 f7[ 	]*vpdpwssds xmm22,xmm19,xmm23
+[ 	]*[a-f0-9]+:[ 	]*62 a2 65 07 53 f7[ 	]*vpdpwssds xmm22\{k7\},xmm19,xmm23
+[ 	]*[a-f0-9]+:[ 	]*62 a2 65 87 53 f7[ 	]*vpdpwssds xmm22\{k7\}\{z\},xmm19,xmm23
+[ 	]*[a-f0-9]+:[ 	]*62 a2 65 00 53 b4 f0 23 01 00 00[ 	]*vpdpwssds xmm22,xmm19,XMMWORD PTR \[rax\+r14\*8\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 65 00 53 72 7f[ 	]*vpdpwssds xmm22,xmm19,XMMWORD PTR \[rdx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 65 10 53 72 7f[ 	]*vpdpwssds xmm22,xmm19,DWORD PTR \[rdx\+0x1fc\]\{1to4\}
+[ 	]*[a-f0-9]+:[ 	]*62 82 45 20 53 fc[ 	]*vpdpwssds ymm23,ymm23,ymm28
+[ 	]*[a-f0-9]+:[ 	]*62 82 45 23 53 fc[ 	]*vpdpwssds ymm23\{k3\},ymm23,ymm28
+[ 	]*[a-f0-9]+:[ 	]*62 82 45 a3 53 fc[ 	]*vpdpwssds ymm23\{k3\}\{z\},ymm23,ymm28
+[ 	]*[a-f0-9]+:[ 	]*62 a2 45 20 53 bc f0 23 01 00 00[ 	]*vpdpwssds ymm23,ymm23,YMMWORD PTR \[rax\+r14\*8\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 45 20 53 7a 7f[ 	]*vpdpwssds ymm23,ymm23,YMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 45 30 53 7a 7f[ 	]*vpdpwssds ymm23,ymm23,DWORD PTR \[rdx\+0x1fc\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 82 15 00 50 d4[ 	]*vpdpbusd xmm18,xmm29,xmm28
+[ 	]*[a-f0-9]+:[ 	]*62 82 15 03 50 d4[ 	]*vpdpbusd xmm18\{k3\},xmm29,xmm28
+[ 	]*[a-f0-9]+:[ 	]*62 82 15 83 50 d4[ 	]*vpdpbusd xmm18\{k3\}\{z\},xmm29,xmm28
+[ 	]*[a-f0-9]+:[ 	]*62 a2 15 00 50 94 f0 23 01 00 00[ 	]*vpdpbusd xmm18,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 15 00 50 52 7f[ 	]*vpdpbusd xmm18,xmm29,XMMWORD PTR \[rdx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 15 10 50 52 7f[ 	]*vpdpbusd xmm18,xmm29,DWORD PTR \[rdx\+0x1fc\]\{1to4\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d 20 50 e1[ 	]*vpdpbusd ymm20,ymm18,ymm17
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d 22 50 e1[ 	]*vpdpbusd ymm20\{k2\},ymm18,ymm17
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d a2 50 e1[ 	]*vpdpbusd ymm20\{k2\}\{z\},ymm18,ymm17
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d 20 50 a4 f0 23 01 00 00[ 	]*vpdpbusd ymm20,ymm18,YMMWORD PTR \[rax\+r14\*8\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 6d 20 50 62 7f[ 	]*vpdpbusd ymm20,ymm18,YMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 6d 30 50 62 7f[ 	]*vpdpbusd ymm20,ymm18,DWORD PTR \[rdx\+0x1fc\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 2d 00 51 c3[ 	]*vpdpbusds xmm24,xmm26,xmm27
+[ 	]*[a-f0-9]+:[ 	]*62 02 2d 04 51 c3[ 	]*vpdpbusds xmm24\{k4\},xmm26,xmm27
+[ 	]*[a-f0-9]+:[ 	]*62 02 2d 84 51 c3[ 	]*vpdpbusds xmm24\{k4\}\{z\},xmm26,xmm27
+[ 	]*[a-f0-9]+:[ 	]*62 22 2d 00 51 84 f0 23 01 00 00[ 	]*vpdpbusds xmm24,xmm26,XMMWORD PTR \[rax\+r14\*8\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 2d 00 51 42 7f[ 	]*vpdpbusds xmm24,xmm26,XMMWORD PTR \[rdx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 2d 10 51 42 7f[ 	]*vpdpbusds xmm24,xmm26,DWORD PTR \[rdx\+0x1fc\]\{1to4\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 15 20 51 f1[ 	]*vpdpbusds ymm30,ymm29,ymm25
+[ 	]*[a-f0-9]+:[ 	]*62 02 15 21 51 f1[ 	]*vpdpbusds ymm30\{k1\},ymm29,ymm25
+[ 	]*[a-f0-9]+:[ 	]*62 02 15 a1 51 f1[ 	]*vpdpbusds ymm30\{k1\}\{z\},ymm29,ymm25
+[ 	]*[a-f0-9]+:[ 	]*62 22 15 20 51 b4 f0 23 01 00 00[ 	]*vpdpbusds ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 15 20 51 72 7f[ 	]*vpdpbusds ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 15 30 51 72 7f[ 	]*vpdpbusds ymm30,ymm29,DWORD PTR \[rdx\+0x1fc\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 5d 00 52 ef[ 	]*vpdpwssd xmm21,xmm20,xmm23
+[ 	]*[a-f0-9]+:[ 	]*62 a2 5d 06 52 ef[ 	]*vpdpwssd xmm21\{k6\},xmm20,xmm23
+[ 	]*[a-f0-9]+:[ 	]*62 a2 5d 86 52 ef[ 	]*vpdpwssd xmm21\{k6\}\{z\},xmm20,xmm23
+[ 	]*[a-f0-9]+:[ 	]*62 a2 5d 00 52 ac f0 34 12 00 00[ 	]*vpdpwssd xmm21,xmm20,XMMWORD PTR \[rax\+r14\*8\+0x1234\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 5d 00 52 6a 7f[ 	]*vpdpwssd xmm21,xmm20,XMMWORD PTR \[rdx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 5d 10 52 6a 7f[ 	]*vpdpwssd xmm21,xmm20,DWORD PTR \[rdx\+0x1fc\]\{1to4\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 20 52 c9[ 	]*vpdpwssd ymm25,ymm27,ymm17
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 26 52 c9[ 	]*vpdpwssd ymm25\{k6\},ymm27,ymm17
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 a6 52 c9[ 	]*vpdpwssd ymm25\{k6\}\{z\},ymm27,ymm17
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 20 52 8c f0 34 12 00 00[ 	]*vpdpwssd ymm25,ymm27,YMMWORD PTR \[rax\+r14\*8\+0x1234\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 25 20 52 4a 7f[ 	]*vpdpwssd ymm25,ymm27,YMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 25 30 52 4a 7f[ 	]*vpdpwssd ymm25,ymm27,DWORD PTR \[rdx\+0x1fc\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 35 00 53 f5[ 	]*vpdpwssds xmm30,xmm25,xmm21
+[ 	]*[a-f0-9]+:[ 	]*62 22 35 06 53 f5[ 	]*vpdpwssds xmm30\{k6\},xmm25,xmm21
+[ 	]*[a-f0-9]+:[ 	]*62 22 35 86 53 f5[ 	]*vpdpwssds xmm30\{k6\}\{z\},xmm25,xmm21
+[ 	]*[a-f0-9]+:[ 	]*62 22 35 00 53 b4 f0 34 12 00 00[ 	]*vpdpwssds xmm30,xmm25,XMMWORD PTR \[rax\+r14\*8\+0x1234\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 35 00 53 72 7f[ 	]*vpdpwssds xmm30,xmm25,XMMWORD PTR \[rdx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 35 10 53 72 7f[ 	]*vpdpwssds xmm30,xmm25,DWORD PTR \[rdx\+0x1fc\]\{1to4\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 25 20 53 e3[ 	]*vpdpwssds ymm28,ymm27,ymm27
+[ 	]*[a-f0-9]+:[ 	]*62 02 25 27 53 e3[ 	]*vpdpwssds ymm28\{k7\},ymm27,ymm27
+[ 	]*[a-f0-9]+:[ 	]*62 02 25 a7 53 e3[ 	]*vpdpwssds ymm28\{k7\}\{z\},ymm27,ymm27
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 20 53 a4 f0 34 12 00 00[ 	]*vpdpwssds ymm28,ymm27,YMMWORD PTR \[rax\+r14\*8\+0x1234\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 25 20 53 62 7f[ 	]*vpdpwssds ymm28,ymm27,YMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 25 30 53 62 7f[ 	]*vpdpwssds ymm28,ymm27,DWORD PTR \[rdx\+0x1fc\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 6d 00 50 d3[ 	]*vpdpbusd xmm26,xmm18,xmm19
+[ 	]*[a-f0-9]+:[ 	]*62 22 6d 06 50 d3[ 	]*vpdpbusd xmm26\{k6\},xmm18,xmm19
+[ 	]*[a-f0-9]+:[ 	]*62 22 6d 86 50 d3[ 	]*vpdpbusd xmm26\{k6\}\{z\},xmm18,xmm19
+[ 	]*[a-f0-9]+:[ 	]*62 22 6d 00 50 94 f0 34 12 00 00[ 	]*vpdpbusd xmm26,xmm18,XMMWORD PTR \[rax\+r14\*8\+0x1234\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 6d 00 50 52 7f[ 	]*vpdpbusd xmm26,xmm18,XMMWORD PTR \[rdx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 6d 10 50 52 7f[ 	]*vpdpbusd xmm26,xmm18,DWORD PTR \[rdx\+0x1fc\]\{1to4\}
+[ 	]*[a-f0-9]+:[ 	]*62 82 75 20 50 eb[ 	]*vpdpbusd ymm21,ymm17,ymm27
+[ 	]*[a-f0-9]+:[ 	]*62 82 75 22 50 eb[ 	]*vpdpbusd ymm21\{k2\},ymm17,ymm27
+[ 	]*[a-f0-9]+:[ 	]*62 82 75 a2 50 eb[ 	]*vpdpbusd ymm21\{k2\}\{z\},ymm17,ymm27
+[ 	]*[a-f0-9]+:[ 	]*62 a2 75 20 50 ac f0 34 12 00 00[ 	]*vpdpbusd ymm21,ymm17,YMMWORD PTR \[rax\+r14\*8\+0x1234\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 75 20 50 6a 7f[ 	]*vpdpbusd ymm21,ymm17,YMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 75 30 50 6a 7f[ 	]*vpdpbusd ymm21,ymm17,DWORD PTR \[rdx\+0x1fc\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 2d 00 51 e0[ 	]*vpdpbusds xmm28,xmm26,xmm24
+[ 	]*[a-f0-9]+:[ 	]*62 02 2d 01 51 e0[ 	]*vpdpbusds xmm28\{k1\},xmm26,xmm24
+[ 	]*[a-f0-9]+:[ 	]*62 02 2d 81 51 e0[ 	]*vpdpbusds xmm28\{k1\}\{z\},xmm26,xmm24
+[ 	]*[a-f0-9]+:[ 	]*62 22 2d 00 51 a4 f0 34 12 00 00[ 	]*vpdpbusds xmm28,xmm26,XMMWORD PTR \[rax\+r14\*8\+0x1234\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 2d 00 51 62 7f[ 	]*vpdpbusds xmm28,xmm26,XMMWORD PTR \[rdx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 2d 10 51 62 7f[ 	]*vpdpbusds xmm28,xmm26,DWORD PTR \[rdx\+0x1fc\]\{1to4\}
+[ 	]*[a-f0-9]+:[ 	]*62 82 6d 20 51 fb[ 	]*vpdpbusds ymm23,ymm18,ymm27
+[ 	]*[a-f0-9]+:[ 	]*62 82 6d 26 51 fb[ 	]*vpdpbusds ymm23\{k6\},ymm18,ymm27
+[ 	]*[a-f0-9]+:[ 	]*62 82 6d a6 51 fb[ 	]*vpdpbusds ymm23\{k6\}\{z\},ymm18,ymm27
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d 20 51 bc f0 34 12 00 00[ 	]*vpdpbusds ymm23,ymm18,YMMWORD PTR \[rax\+r14\*8\+0x1234\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 6d 20 51 7a 7f[ 	]*vpdpbusds ymm23,ymm18,YMMWORD PTR \[rdx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 e2 6d 30 51 7a 7f[ 	]*vpdpbusds ymm23,ymm18,DWORD PTR \[rdx\+0x1fc\]\{1to8\}
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512vnni_vl.d b/gas/testsuite/gas/i386/x86-64-avx512vnni_vl.d
new file mode 100644
index 0000000000..2817562041
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512vnni_vl.d
@@ -0,0 +1,108 @@
+#as:
+#objdump: -dw
+#name: x86_64 AVX512VNNI/VL insns
+#source: x86-64-avx512vnni_vl.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 22 4d 00 52 d4[ 	]*vpdpwssd %xmm20,%xmm22,%xmm26
+[ 	]*[a-f0-9]+:[ 	]*62 22 4d 03 52 d4[ 	]*vpdpwssd %xmm20,%xmm22,%xmm26\{%k3\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 4d 83 52 d4[ 	]*vpdpwssd %xmm20,%xmm22,%xmm26\{%k3\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 4d 00 52 94 f0 23 01 00 00[ 	]*vpdpwssd 0x123\(%rax,%r14,8\),%xmm22,%xmm26
+[ 	]*[a-f0-9]+:[ 	]*62 62 4d 00 52 52 7f[ 	]*vpdpwssd 0x7f0\(%rdx\),%xmm22,%xmm26
+[ 	]*[a-f0-9]+:[ 	]*62 62 4d 10 52 52 7f[ 	]*vpdpwssd 0x1fc\(%rdx\)\{1to4\},%xmm22,%xmm26
+[ 	]*[a-f0-9]+:[ 	]*62 a2 5d 20 52 e2[ 	]*vpdpwssd %ymm18,%ymm20,%ymm20
+[ 	]*[a-f0-9]+:[ 	]*62 a2 5d 25 52 e2[ 	]*vpdpwssd %ymm18,%ymm20,%ymm20\{%k5\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 5d a5 52 e2[ 	]*vpdpwssd %ymm18,%ymm20,%ymm20\{%k5\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 5d 20 52 a4 f0 23 01 00 00[ 	]*vpdpwssd 0x123\(%rax,%r14,8\),%ymm20,%ymm20
+[ 	]*[a-f0-9]+:[ 	]*62 e2 5d 20 52 62 7f[ 	]*vpdpwssd 0xfe0\(%rdx\),%ymm20,%ymm20
+[ 	]*[a-f0-9]+:[ 	]*62 e2 5d 30 52 62 7f[ 	]*vpdpwssd 0x1fc\(%rdx\)\{1to8\},%ymm20,%ymm20
+[ 	]*[a-f0-9]+:[ 	]*62 a2 65 00 53 f7[ 	]*vpdpwssds %xmm23,%xmm19,%xmm22
+[ 	]*[a-f0-9]+:[ 	]*62 a2 65 07 53 f7[ 	]*vpdpwssds %xmm23,%xmm19,%xmm22\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 65 87 53 f7[ 	]*vpdpwssds %xmm23,%xmm19,%xmm22\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 65 00 53 b4 f0 23 01 00 00[ 	]*vpdpwssds 0x123\(%rax,%r14,8\),%xmm19,%xmm22
+[ 	]*[a-f0-9]+:[ 	]*62 e2 65 00 53 72 7f[ 	]*vpdpwssds 0x7f0\(%rdx\),%xmm19,%xmm22
+[ 	]*[a-f0-9]+:[ 	]*62 e2 65 10 53 72 7f[ 	]*vpdpwssds 0x1fc\(%rdx\)\{1to4\},%xmm19,%xmm22
+[ 	]*[a-f0-9]+:[ 	]*62 82 45 20 53 fc[ 	]*vpdpwssds %ymm28,%ymm23,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 82 45 23 53 fc[ 	]*vpdpwssds %ymm28,%ymm23,%ymm23\{%k3\}
+[ 	]*[a-f0-9]+:[ 	]*62 82 45 a3 53 fc[ 	]*vpdpwssds %ymm28,%ymm23,%ymm23\{%k3\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 45 20 53 bc f0 23 01 00 00[ 	]*vpdpwssds 0x123\(%rax,%r14,8\),%ymm23,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 e2 45 20 53 7a 7f[ 	]*vpdpwssds 0xfe0\(%rdx\),%ymm23,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 e2 45 30 53 7a 7f[ 	]*vpdpwssds 0x1fc\(%rdx\)\{1to8\},%ymm23,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 82 15 00 50 d4[ 	]*vpdpbusd %xmm28,%xmm29,%xmm18
+[ 	]*[a-f0-9]+:[ 	]*62 82 15 03 50 d4[ 	]*vpdpbusd %xmm28,%xmm29,%xmm18\{%k3\}
+[ 	]*[a-f0-9]+:[ 	]*62 82 15 83 50 d4[ 	]*vpdpbusd %xmm28,%xmm29,%xmm18\{%k3\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 15 00 50 94 f0 23 01 00 00[ 	]*vpdpbusd 0x123\(%rax,%r14,8\),%xmm29,%xmm18
+[ 	]*[a-f0-9]+:[ 	]*62 e2 15 00 50 52 7f[ 	]*vpdpbusd 0x7f0\(%rdx\),%xmm29,%xmm18
+[ 	]*[a-f0-9]+:[ 	]*62 e2 15 10 50 52 7f[ 	]*vpdpbusd 0x1fc\(%rdx\)\{1to4\},%xmm29,%xmm18
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d 20 50 e1[ 	]*vpdpbusd %ymm17,%ymm18,%ymm20
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d 22 50 e1[ 	]*vpdpbusd %ymm17,%ymm18,%ymm20\{%k2\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d a2 50 e1[ 	]*vpdpbusd %ymm17,%ymm18,%ymm20\{%k2\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d 20 50 a4 f0 23 01 00 00[ 	]*vpdpbusd 0x123\(%rax,%r14,8\),%ymm18,%ymm20
+[ 	]*[a-f0-9]+:[ 	]*62 e2 6d 20 50 62 7f[ 	]*vpdpbusd 0xfe0\(%rdx\),%ymm18,%ymm20
+[ 	]*[a-f0-9]+:[ 	]*62 e2 6d 30 50 62 7f[ 	]*vpdpbusd 0x1fc\(%rdx\)\{1to8\},%ymm18,%ymm20
+[ 	]*[a-f0-9]+:[ 	]*62 02 2d 00 51 c3[ 	]*vpdpbusds %xmm27,%xmm26,%xmm24
+[ 	]*[a-f0-9]+:[ 	]*62 02 2d 04 51 c3[ 	]*vpdpbusds %xmm27,%xmm26,%xmm24\{%k4\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 2d 84 51 c3[ 	]*vpdpbusds %xmm27,%xmm26,%xmm24\{%k4\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 2d 00 51 84 f0 23 01 00 00[ 	]*vpdpbusds 0x123\(%rax,%r14,8\),%xmm26,%xmm24
+[ 	]*[a-f0-9]+:[ 	]*62 62 2d 00 51 42 7f[ 	]*vpdpbusds 0x7f0\(%rdx\),%xmm26,%xmm24
+[ 	]*[a-f0-9]+:[ 	]*62 62 2d 10 51 42 7f[ 	]*vpdpbusds 0x1fc\(%rdx\)\{1to4\},%xmm26,%xmm24
+[ 	]*[a-f0-9]+:[ 	]*62 02 15 20 51 f1[ 	]*vpdpbusds %ymm25,%ymm29,%ymm30
+[ 	]*[a-f0-9]+:[ 	]*62 02 15 21 51 f1[ 	]*vpdpbusds %ymm25,%ymm29,%ymm30\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 15 a1 51 f1[ 	]*vpdpbusds %ymm25,%ymm29,%ymm30\{%k1\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 15 20 51 b4 f0 23 01 00 00[ 	]*vpdpbusds 0x123\(%rax,%r14,8\),%ymm29,%ymm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 15 20 51 72 7f[ 	]*vpdpbusds 0xfe0\(%rdx\),%ymm29,%ymm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 15 30 51 72 7f[ 	]*vpdpbusds 0x1fc\(%rdx\)\{1to8\},%ymm29,%ymm30
+[ 	]*[a-f0-9]+:[ 	]*62 a2 5d 00 52 ef[ 	]*vpdpwssd %xmm23,%xmm20,%xmm21
+[ 	]*[a-f0-9]+:[ 	]*62 a2 5d 06 52 ef[ 	]*vpdpwssd %xmm23,%xmm20,%xmm21\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 5d 86 52 ef[ 	]*vpdpwssd %xmm23,%xmm20,%xmm21\{%k6\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 5d 00 52 ac f0 34 12 00 00[ 	]*vpdpwssd 0x1234\(%rax,%r14,8\),%xmm20,%xmm21
+[ 	]*[a-f0-9]+:[ 	]*62 e2 5d 00 52 6a 7f[ 	]*vpdpwssd 0x7f0\(%rdx\),%xmm20,%xmm21
+[ 	]*[a-f0-9]+:[ 	]*62 e2 5d 10 52 6a 7f[ 	]*vpdpwssd 0x1fc\(%rdx\)\{1to4\},%xmm20,%xmm21
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 20 52 c9[ 	]*vpdpwssd %ymm17,%ymm27,%ymm25
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 26 52 c9[ 	]*vpdpwssd %ymm17,%ymm27,%ymm25\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 a6 52 c9[ 	]*vpdpwssd %ymm17,%ymm27,%ymm25\{%k6\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 20 52 8c f0 34 12 00 00[ 	]*vpdpwssd 0x1234\(%rax,%r14,8\),%ymm27,%ymm25
+[ 	]*[a-f0-9]+:[ 	]*62 62 25 20 52 4a 7f[ 	]*vpdpwssd 0xfe0\(%rdx\),%ymm27,%ymm25
+[ 	]*[a-f0-9]+:[ 	]*62 62 25 30 52 4a 7f[ 	]*vpdpwssd 0x1fc\(%rdx\)\{1to8\},%ymm27,%ymm25
+[ 	]*[a-f0-9]+:[ 	]*62 22 35 00 53 f5[ 	]*vpdpwssds %xmm21,%xmm25,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 22 35 06 53 f5[ 	]*vpdpwssds %xmm21,%xmm25,%xmm30\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 35 86 53 f5[ 	]*vpdpwssds %xmm21,%xmm25,%xmm30\{%k6\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 35 00 53 b4 f0 34 12 00 00[ 	]*vpdpwssds 0x1234\(%rax,%r14,8\),%xmm25,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 35 00 53 72 7f[ 	]*vpdpwssds 0x7f0\(%rdx\),%xmm25,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 35 10 53 72 7f[ 	]*vpdpwssds 0x1fc\(%rdx\)\{1to4\},%xmm25,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 02 25 20 53 e3[ 	]*vpdpwssds %ymm27,%ymm27,%ymm28
+[ 	]*[a-f0-9]+:[ 	]*62 02 25 27 53 e3[ 	]*vpdpwssds %ymm27,%ymm27,%ymm28\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 25 a7 53 e3[ 	]*vpdpwssds %ymm27,%ymm27,%ymm28\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 25 20 53 a4 f0 34 12 00 00[ 	]*vpdpwssds 0x1234\(%rax,%r14,8\),%ymm27,%ymm28
+[ 	]*[a-f0-9]+:[ 	]*62 62 25 20 53 62 7f[ 	]*vpdpwssds 0xfe0\(%rdx\),%ymm27,%ymm28
+[ 	]*[a-f0-9]+:[ 	]*62 62 25 30 53 62 7f[ 	]*vpdpwssds 0x1fc\(%rdx\)\{1to8\},%ymm27,%ymm28
+[ 	]*[a-f0-9]+:[ 	]*62 22 6d 00 50 d3[ 	]*vpdpbusd %xmm19,%xmm18,%xmm26
+[ 	]*[a-f0-9]+:[ 	]*62 22 6d 06 50 d3[ 	]*vpdpbusd %xmm19,%xmm18,%xmm26\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 6d 86 50 d3[ 	]*vpdpbusd %xmm19,%xmm18,%xmm26\{%k6\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 6d 00 50 94 f0 34 12 00 00[ 	]*vpdpbusd 0x1234\(%rax,%r14,8\),%xmm18,%xmm26
+[ 	]*[a-f0-9]+:[ 	]*62 62 6d 00 50 52 7f[ 	]*vpdpbusd 0x7f0\(%rdx\),%xmm18,%xmm26
+[ 	]*[a-f0-9]+:[ 	]*62 62 6d 10 50 52 7f[ 	]*vpdpbusd 0x1fc\(%rdx\)\{1to4\},%xmm18,%xmm26
+[ 	]*[a-f0-9]+:[ 	]*62 82 75 20 50 eb[ 	]*vpdpbusd %ymm27,%ymm17,%ymm21
+[ 	]*[a-f0-9]+:[ 	]*62 82 75 22 50 eb[ 	]*vpdpbusd %ymm27,%ymm17,%ymm21\{%k2\}
+[ 	]*[a-f0-9]+:[ 	]*62 82 75 a2 50 eb[ 	]*vpdpbusd %ymm27,%ymm17,%ymm21\{%k2\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 75 20 50 ac f0 34 12 00 00[ 	]*vpdpbusd 0x1234\(%rax,%r14,8\),%ymm17,%ymm21
+[ 	]*[a-f0-9]+:[ 	]*62 e2 75 20 50 6a 7f[ 	]*vpdpbusd 0xfe0\(%rdx\),%ymm17,%ymm21
+[ 	]*[a-f0-9]+:[ 	]*62 e2 75 30 50 6a 7f[ 	]*vpdpbusd 0x1fc\(%rdx\)\{1to8\},%ymm17,%ymm21
+[ 	]*[a-f0-9]+:[ 	]*62 02 2d 00 51 e0[ 	]*vpdpbusds %xmm24,%xmm26,%xmm28
+[ 	]*[a-f0-9]+:[ 	]*62 02 2d 01 51 e0[ 	]*vpdpbusds %xmm24,%xmm26,%xmm28\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 2d 81 51 e0[ 	]*vpdpbusds %xmm24,%xmm26,%xmm28\{%k1\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 22 2d 00 51 a4 f0 34 12 00 00[ 	]*vpdpbusds 0x1234\(%rax,%r14,8\),%xmm26,%xmm28
+[ 	]*[a-f0-9]+:[ 	]*62 62 2d 00 51 62 7f[ 	]*vpdpbusds 0x7f0\(%rdx\),%xmm26,%xmm28
+[ 	]*[a-f0-9]+:[ 	]*62 62 2d 10 51 62 7f[ 	]*vpdpbusds 0x1fc\(%rdx\)\{1to4\},%xmm26,%xmm28
+[ 	]*[a-f0-9]+:[ 	]*62 82 6d 20 51 fb[ 	]*vpdpbusds %ymm27,%ymm18,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 82 6d 26 51 fb[ 	]*vpdpbusds %ymm27,%ymm18,%ymm23\{%k6\}
+[ 	]*[a-f0-9]+:[ 	]*62 82 6d a6 51 fb[ 	]*vpdpbusds %ymm27,%ymm18,%ymm23\{%k6\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d 20 51 bc f0 34 12 00 00[ 	]*vpdpbusds 0x1234\(%rax,%r14,8\),%ymm18,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 e2 6d 20 51 7a 7f[ 	]*vpdpbusds 0xfe0\(%rdx\),%ymm18,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 e2 6d 30 51 7a 7f[ 	]*vpdpbusds 0x1fc\(%rdx\)\{1to8\},%ymm18,%ymm23
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512vnni_vl.s b/gas/testsuite/gas/i386/x86-64-avx512vnni_vl.s
new file mode 100644
index 0000000000..9c85ac7b15
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512vnni_vl.s
@@ -0,0 +1,109 @@
+# Check 64bit AVX512{VNNI,VL} instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vpdpwssd	%xmm20, %xmm22, %xmm26	 # AVX512{VNNI,VL}
+	vpdpwssd	%xmm20, %xmm22, %xmm26{%k3}	 # AVX512{VNNI,VL}
+	vpdpwssd	%xmm20, %xmm22, %xmm26{%k3}{z}	 # AVX512{VNNI,VL}
+	vpdpwssd	0x123(%rax,%r14,8), %xmm22, %xmm26	 # AVX512{VNNI,VL}
+	vpdpwssd	2032(%rdx), %xmm22, %xmm26	 # AVX512{VNNI,VL} Disp8
+	vpdpwssd	508(%rdx){1to4}, %xmm22, %xmm26	 # AVX512{VNNI,VL} Disp8
+	vpdpwssd	%ymm18, %ymm20, %ymm20	 # AVX512{VNNI,VL}
+	vpdpwssd	%ymm18, %ymm20, %ymm20{%k5}	 # AVX512{VNNI,VL}
+	vpdpwssd	%ymm18, %ymm20, %ymm20{%k5}{z}	 # AVX512{VNNI,VL}
+	vpdpwssd	0x123(%rax,%r14,8), %ymm20, %ymm20	 # AVX512{VNNI,VL}
+	vpdpwssd	4064(%rdx), %ymm20, %ymm20	 # AVX512{VNNI,VL} Disp8
+	vpdpwssd	508(%rdx){1to8}, %ymm20, %ymm20	 # AVX512{VNNI,VL} Disp8
+
+	vpdpwssds	%xmm23, %xmm19, %xmm22	 # AVX512{VNNI,VL}
+	vpdpwssds	%xmm23, %xmm19, %xmm22{%k7}	 # AVX512{VNNI,VL}
+	vpdpwssds	%xmm23, %xmm19, %xmm22{%k7}{z}	 # AVX512{VNNI,VL}
+	vpdpwssds	0x123(%rax,%r14,8), %xmm19, %xmm22	 # AVX512{VNNI,VL}
+	vpdpwssds	2032(%rdx), %xmm19, %xmm22	 # AVX512{VNNI,VL} Disp8
+	vpdpwssds	508(%rdx){1to4}, %xmm19, %xmm22	 # AVX512{VNNI,VL} Disp8
+	vpdpwssds	%ymm28, %ymm23, %ymm23	 # AVX512{VNNI,VL}
+	vpdpwssds	%ymm28, %ymm23, %ymm23{%k3}	 # AVX512{VNNI,VL}
+	vpdpwssds	%ymm28, %ymm23, %ymm23{%k3}{z}	 # AVX512{VNNI,VL}
+	vpdpwssds	0x123(%rax,%r14,8), %ymm23, %ymm23	 # AVX512{VNNI,VL}
+	vpdpwssds	4064(%rdx), %ymm23, %ymm23	 # AVX512{VNNI,VL} Disp8
+	vpdpwssds	508(%rdx){1to8}, %ymm23, %ymm23	 # AVX512{VNNI,VL} Disp8
+
+	vpdpbusd	%xmm28, %xmm29, %xmm18	 # AVX512{VNNI,VL}
+	vpdpbusd	%xmm28, %xmm29, %xmm18{%k3}	 # AVX512{VNNI,VL}
+	vpdpbusd	%xmm28, %xmm29, %xmm18{%k3}{z}	 # AVX512{VNNI,VL}
+	vpdpbusd	0x123(%rax,%r14,8), %xmm29, %xmm18	 # AVX512{VNNI,VL}
+	vpdpbusd	2032(%rdx), %xmm29, %xmm18	 # AVX512{VNNI,VL} Disp8
+	vpdpbusd	508(%rdx){1to4}, %xmm29, %xmm18	 # AVX512{VNNI,VL} Disp8
+	vpdpbusd	%ymm17, %ymm18, %ymm20	 # AVX512{VNNI,VL}
+	vpdpbusd	%ymm17, %ymm18, %ymm20{%k2}	 # AVX512{VNNI,VL}
+	vpdpbusd	%ymm17, %ymm18, %ymm20{%k2}{z}	 # AVX512{VNNI,VL}
+	vpdpbusd	0x123(%rax,%r14,8), %ymm18, %ymm20	 # AVX512{VNNI,VL}
+	vpdpbusd	4064(%rdx), %ymm18, %ymm20	 # AVX512{VNNI,VL} Disp8
+	vpdpbusd	508(%rdx){1to8}, %ymm18, %ymm20	 # AVX512{VNNI,VL} Disp8
+
+	vpdpbusds	%xmm27, %xmm26, %xmm24	 # AVX512{VNNI,VL}
+	vpdpbusds	%xmm27, %xmm26, %xmm24{%k4}	 # AVX512{VNNI,VL}
+	vpdpbusds	%xmm27, %xmm26, %xmm24{%k4}{z}	 # AVX512{VNNI,VL}
+	vpdpbusds	0x123(%rax,%r14,8), %xmm26, %xmm24	 # AVX512{VNNI,VL}
+	vpdpbusds	2032(%rdx), %xmm26, %xmm24	 # AVX512{VNNI,VL} Disp8
+	vpdpbusds	508(%rdx){1to4}, %xmm26, %xmm24	 # AVX512{VNNI,VL} Disp8
+	vpdpbusds	%ymm25, %ymm29, %ymm30	 # AVX512{VNNI,VL}
+	vpdpbusds	%ymm25, %ymm29, %ymm30{%k1}	 # AVX512{VNNI,VL}
+	vpdpbusds	%ymm25, %ymm29, %ymm30{%k1}{z}	 # AVX512{VNNI,VL}
+	vpdpbusds	0x123(%rax,%r14,8), %ymm29, %ymm30	 # AVX512{VNNI,VL}
+	vpdpbusds	4064(%rdx), %ymm29, %ymm30	 # AVX512{VNNI,VL} Disp8
+	vpdpbusds	508(%rdx){1to8}, %ymm29, %ymm30	 # AVX512{VNNI,VL} Disp8
+
+	.intel_syntax noprefix
+	vpdpwssd	xmm21, xmm20, xmm23	 # AVX512{VNNI,VL}
+	vpdpwssd	xmm21{k6}, xmm20, xmm23	 # AVX512{VNNI,VL}
+	vpdpwssd	xmm21{k6}{z}, xmm20, xmm23	 # AVX512{VNNI,VL}
+	vpdpwssd	xmm21, xmm20, XMMWORD PTR [rax+r14*8+0x1234]	 # AVX512{VNNI,VL}
+	vpdpwssd	xmm21, xmm20, XMMWORD PTR [rdx+2032]	 # AVX512{VNNI,VL} Disp8
+	vpdpwssd	xmm21, xmm20, [rdx+508]{1to4}	 # AVX512{VNNI,VL} Disp8
+	vpdpwssd	ymm25, ymm27, ymm17	 # AVX512{VNNI,VL}
+	vpdpwssd	ymm25{k6}, ymm27, ymm17	 # AVX512{VNNI,VL}
+	vpdpwssd	ymm25{k6}{z}, ymm27, ymm17	 # AVX512{VNNI,VL}
+	vpdpwssd	ymm25, ymm27, YMMWORD PTR [rax+r14*8+0x1234]	 # AVX512{VNNI,VL}
+	vpdpwssd	ymm25, ymm27, YMMWORD PTR [rdx+4064]	 # AVX512{VNNI,VL} Disp8
+	vpdpwssd	ymm25, ymm27, [rdx+508]{1to8}	 # AVX512{VNNI,VL} Disp8
+
+	vpdpwssds	xmm30, xmm25, xmm21	 # AVX512{VNNI,VL}
+	vpdpwssds	xmm30{k6}, xmm25, xmm21	 # AVX512{VNNI,VL}
+	vpdpwssds	xmm30{k6}{z}, xmm25, xmm21	 # AVX512{VNNI,VL}
+	vpdpwssds	xmm30, xmm25, XMMWORD PTR [rax+r14*8+0x1234]	 # AVX512{VNNI,VL}
+	vpdpwssds	xmm30, xmm25, XMMWORD PTR [rdx+2032]	 # AVX512{VNNI,VL} Disp8
+	vpdpwssds	xmm30, xmm25, [rdx+508]{1to4}	 # AVX512{VNNI,VL} Disp8
+	vpdpwssds	ymm28, ymm27, ymm27	 # AVX512{VNNI,VL}
+	vpdpwssds	ymm28{k7}, ymm27, ymm27	 # AVX512{VNNI,VL}
+	vpdpwssds	ymm28{k7}{z}, ymm27, ymm27	 # AVX512{VNNI,VL}
+	vpdpwssds	ymm28, ymm27, YMMWORD PTR [rax+r14*8+0x1234]	 # AVX512{VNNI,VL}
+	vpdpwssds	ymm28, ymm27, YMMWORD PTR [rdx+4064]	 # AVX512{VNNI,VL} Disp8
+	vpdpwssds	ymm28, ymm27, [rdx+508]{1to8}	 # AVX512{VNNI,VL} Disp8
+
+	vpdpbusd	xmm26, xmm18, xmm19	 # AVX512{VNNI,VL}
+	vpdpbusd	xmm26{k6}, xmm18, xmm19	 # AVX512{VNNI,VL}
+	vpdpbusd	xmm26{k6}{z}, xmm18, xmm19	 # AVX512{VNNI,VL}
+	vpdpbusd	xmm26, xmm18, XMMWORD PTR [rax+r14*8+0x1234]	 # AVX512{VNNI,VL}
+	vpdpbusd	xmm26, xmm18, XMMWORD PTR [rdx+2032]	 # AVX512{VNNI,VL} Disp8
+	vpdpbusd	xmm26, xmm18, [rdx+508]{1to4}	 # AVX512{VNNI,VL} Disp8
+	vpdpbusd	ymm21, ymm17, ymm27	 # AVX512{VNNI,VL}
+	vpdpbusd	ymm21{k2}, ymm17, ymm27	 # AVX512{VNNI,VL}
+	vpdpbusd	ymm21{k2}{z}, ymm17, ymm27	 # AVX512{VNNI,VL}
+	vpdpbusd	ymm21, ymm17, YMMWORD PTR [rax+r14*8+0x1234]	 # AVX512{VNNI,VL}
+	vpdpbusd	ymm21, ymm17, YMMWORD PTR [rdx+4064]	 # AVX512{VNNI,VL} Disp8
+	vpdpbusd	ymm21, ymm17, [rdx+508]{1to8}	 # AVX512{VNNI,VL} Disp8
+
+	vpdpbusds	xmm28, xmm26, xmm24	 # AVX512{VNNI,VL}
+	vpdpbusds	xmm28{k1}, xmm26, xmm24	 # AVX512{VNNI,VL}
+	vpdpbusds	xmm28{k1}{z}, xmm26, xmm24	 # AVX512{VNNI,VL}
+	vpdpbusds	xmm28, xmm26, XMMWORD PTR [rax+r14*8+0x1234]	 # AVX512{VNNI,VL}
+	vpdpbusds	xmm28, xmm26, XMMWORD PTR [rdx+2032]	 # AVX512{VNNI,VL} Disp8
+	vpdpbusds	xmm28, xmm26, [rdx+508]{1to4}	 # AVX512{VNNI,VL} Disp8
+	vpdpbusds	ymm23, ymm18, ymm27	 # AVX512{VNNI,VL}
+	vpdpbusds	ymm23{k6}, ymm18, ymm27	 # AVX512{VNNI,VL}
+	vpdpbusds	ymm23{k6}{z}, ymm18, ymm27	 # AVX512{VNNI,VL}
+	vpdpbusds	ymm23, ymm18, YMMWORD PTR [rax+r14*8+0x1234]	 # AVX512{VNNI,VL}
+	vpdpbusds	ymm23, ymm18, YMMWORD PTR [rdx+4064]	 # AVX512{VNNI,VL} Disp8
+	vpdpbusds	ymm23, ymm18, [rdx+508]{1to8}	 # AVX512{VNNI,VL} Disp8
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index ef5c963de3..467a2d3b0d 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -385,8 +385,8 @@ static const struct dis386 evex_table[][256] = {
     { PREFIX_TABLE (PREFIX_EVEX_0F384E) },
     { PREFIX_TABLE (PREFIX_EVEX_0F384F) },
     /* 50 */
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_0F3850) },
+    { PREFIX_TABLE (PREFIX_EVEX_0F3851) },
     { PREFIX_TABLE (PREFIX_EVEX_0F3852) },
     { PREFIX_TABLE (PREFIX_EVEX_0F3853) },
     { Bad_Opcode },
@@ -2005,18 +2005,30 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { "vrsqrt14s%XW",	{ XMScalar, VexScalar, EXxmm_mdq }, 0 },
   },
-  /* PREFIX_EVEX_0F3852 */
+  /* PREFIX_EVEX_0F3850 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "vpdpbusd",	{ XM, Vex, EXx }, 0 },
+  },
+  /* PREFIX_EVEX_0F3851 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
+    { "vpdpbusds",	{ XM, Vex, EXx }, 0 },
+  },
+  /* PREFIX_EVEX_0F3852 */
+  {
+    { Bad_Opcode },
     { Bad_Opcode },
+    { "vpdpwssd",	{ XM, Vex, EXx }, 0 },
     { "vp4dpwssd",	{ XM, Vex, EXxmm }, 0 },
   },
   /* PREFIX_EVEX_0F3853 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
+    { "vpdpwssds",	{ XM, Vex, EXx }, 0 },
     { "vp4dpwssds",	{ XM, Vex, EXxmm }, 0 },
   },
   /* PREFIX_EVEX_0F3855 */
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 7f3b18f709..637fce398d 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1572,6 +1572,8 @@ enum
   PREFIX_EVEX_0F384D,
   PREFIX_EVEX_0F384E,
   PREFIX_EVEX_0F384F,
+  PREFIX_EVEX_0F3850,
+  PREFIX_EVEX_0F3851,
   PREFIX_EVEX_0F3852,
   PREFIX_EVEX_0F3853,
   PREFIX_EVEX_0F3855,
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index c04b36486a..1202376a50 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -225,6 +225,8 @@ static initializer cpu_flag_init[] =
     "CPU_AVX512F_FLAGS|CpuAVX512_VPOPCNTDQ" },
   { "CPU_AVX512_VBMI2_FLAGS",
     "CPU_AVX512F_FLAGS|CpuAVX512_VBMI2" },
+  { "CPU_AVX512_VNNI_FLAGS",
+    "CPU_AVX512F_FLAGS|CpuAVX512_VNNI" },
   { "CPU_L1OM_FLAGS",
     "unknown" },
   { "CPU_K1OM_FLAGS",
@@ -300,7 +302,7 @@ static initializer cpu_flag_init[] =
   { "CPU_ANY_AVX2_FLAGS",
     "CpuAVX2" },
   { "CPU_ANY_AVX512F_FLAGS",
-    "CpuVREX|CpuRegZMM|CpuRegMask|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512F" },
+    "CpuVREX|CpuRegZMM|CpuRegMask|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512F" },
   { "CPU_ANY_AVX512CD_FLAGS",
     "CpuAVX512CD" },
   { "CPU_ANY_AVX512ER_FLAGS",
@@ -325,6 +327,8 @@ static initializer cpu_flag_init[] =
     "CpuAVX512_VPOPCNTDQ" },
   { "CPU_ANY_AVX512_VBMI2_FLAGS",
     "CpuAVX512_VBMI2" },
+  { "CPU_ANY_AVX512_VNNI_FLAGS",
+    "CpuAVX512_VNNI" },
 };
 
 static initializer operand_type_init[] =
@@ -532,6 +536,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuAVX512_4VNNIW),
   BITFIELD (CpuAVX512_VPOPCNTDQ),
   BITFIELD (CpuAVX512_VBMI2),
+  BITFIELD (CpuAVX512_VNNI),
   BITFIELD (CpuMWAITX),
   BITFIELD (CpuCLZERO),
   BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index a14f66d525..34b57f5f71 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -200,6 +200,8 @@ enum
   CpuAVX512_VPOPCNTDQ,
   /* Intel AVX-512 VBMI2 Instructions support required.  */
   CpuAVX512_VBMI2,
+  /* Intel AVX-512 VNNI Instructions support required.  */
+  CpuAVX512_VNNI,
   /* mwaitx instruction required */
   CpuMWAITX,
   /* Clzero instruction required */
@@ -243,7 +245,7 @@ enum
 
 /* If you get a compiler error for zero width of the unused field,
    comment it out.  */
- #define CpuUnused	(CpuMax + 1)
+#define CpuUnused	(CpuMax + 1)
 
 /* We can check if an instruction is available with array instead
    of bitfield. */
@@ -335,6 +337,7 @@ typedef union i386_cpu_flags
       unsigned int cpuavx512_4vnniw:1;
       unsigned int cpuavx512_vpopcntdq:1;
       unsigned int cpuavx512_vbmi2:1;
+      unsigned int cpuavx512_vnni:1;
       unsigned int cpumwaitx:1;
       unsigned int cpuclzero:1;
       unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 0dcc17b511..6b7dea76b5 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -6075,6 +6075,26 @@ vpshrdw, 4, 0x6672, None, 1, CpuAVX512_VBMI2|CpuAVX512VL, Modrm|EVex=3|Masking=3
 
 // AVX512_VBMI2 instructions end
 
+// AVX512_VNNI instructions
+
+vpdpbusd, 3, 0x6650, None, 1, CpuAVX512_VNNI, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
+vpdpbusd, 3, 0x6650, None, 1, CpuAVX512_VNNI|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
+vpdpbusd, 3, 0x6650, None, 1, CpuAVX512_VNNI|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
+
+vpdpbusds, 3, 0x6651, None, 1, CpuAVX512_VNNI, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
+vpdpbusds, 3, 0x6651, None, 1, CpuAVX512_VNNI|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
+vpdpbusds, 3, 0x6651, None, 1, CpuAVX512_VNNI|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
+
+vpdpwssd, 3, 0x6652, None, 1, CpuAVX512_VNNI, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
+vpdpwssd, 3, 0x6652, None, 1, CpuAVX512_VNNI|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
+vpdpwssd, 3, 0x6652, None, 1, CpuAVX512_VNNI|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
+
+vpdpwssds, 3, 0x6653, None, 1, CpuAVX512_VNNI, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
+vpdpwssds, 3, 0x6653, None, 1, CpuAVX512_VNNI|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
+vpdpwssds, 3, 0x6653, None, 1, CpuAVX512_VNNI|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
+
+// AVX512_VNNI instructions end
+
 // AVX512 + GFNI instructions
 
 vgf2p8affineinvqb, 4, 0x66cf, None, 1, CpuAVX512F|CpuGFNI, Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }