diff options
| author | Jakob Unterwurzacher <jakob.unterwurzacher@cherry.de> | 2025-06-30 09:50:44 +0200 |
|---|---|---|
| committer | Jakob Unterwurzacher <jakob.unterwurzacher@cherry.de> | 2025-06-30 10:13:53 +0200 |
| commit | d98090bf736b630667a907bbeefbcc0412a2d109 (patch) | |
| tree | 30fcd5efae0cab2463b8b796be60b0ab060d3710 | |
| parent | 65d710f7ca3a09b68cdd2b84a5cb0e7dd517f6ff (diff) | |
TSD: arm64: dts: rockchip: reduce m25p40 spi nor flash freq on ringneck-haikouHEADv6.6.39-ringneck
spi-max-frequency was set to 75MHz, which actually gets you 50MHz on the
bus as verified with an oscilloscope.
At 50MHz, data transfers are flakey with some q7 connector savers.
Running a flashcp loop throws verify errors every now and then.
Reduce freq to 10MHz which is stable also with the q7 connector saver.
Note that this is needed *in addition* to the spi1 cs-gpios fix.
Relates-to: HWIT-490
Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@cherry.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts index a8f52af77097..fd3688152387 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts @@ -219,7 +219,7 @@ m25p40@0 { compatible = "m25p40", "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <75000000>; + spi-max-frequency = <10000000>; #address-cells = <1>; #size-cells = <1>; }; |