summaryrefslogtreecommitdiff
path: root/board/renesas/rsk7203/lowlevel_init.S
blob: 7b9ecd89c318d1821c47b3862054e3e1921210b5 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
/*
 * Copyright (C) 2008 Nobuhiro Iwamatsu
 * Copyright (C) 2008 Renesas Solutions Corp.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <config.h>
#include <version.h>

#include <asm/processor.h>
#include <asm/macro.h>

	.global	lowlevel_init

	.text
	.align	2

lowlevel_init:
	/* Cache setting */
	write32	CCR1_A ,CCR1_D

	/* ConfigurePortPins */
	write16	PECRL3_A, PECRL3_D

	write16	PCCRL4_A, PCCRL4_D0

	write16	PECRL4_A, PECRL4_D0

	write16	PEIORL_A, PEIORL_D0

	write16	PCIORL_A, PCIORL_D

	write16	PFCRH2_A, PFCRH2_D

	write16	PFCRH3_A, PFCRH3_D

	write16	PFCRH1_A, PFCRH1_D

	write16	PFIORH_A, PFIORH_D

	write16	PECRL1_A, PECRL1_D0

	write16	PEIORL_A, PEIORL_D1

	/* Configure Operating Frequency */
	write16	WTCSR_A, WTCSR_D0

	write16	WTCSR_A, WTCSR_D1

	write16	WTCNT_A, WTCNT_D

	/* Set clock mode*/
	write16	FRQCR_A, FRQCR_D

	/* Configure Bus And Memory */
init_bsc_cs0:
	write16	PCCRL4_A, PCCRL4_D1

	write16	PECRL1_A, PECRL1_D1

	write32	CMNCR_A, CMNCR_D

	write32	SC0BCR_A, SC0BCR_D

	write32	CS0WCR_A, CS0WCR_D

init_bsc_cs1:
	write16	PECRL4_A, PECRL4_D1

	write32	CS1WCR_A, CS1WCR_D

init_sdram:
	write16	PCCRL2_A, PCCRL2_D

	write16	PCCRL4_A, PCCRL4_D2

	write16	PCCRL1_A, PCCRL1_D

	write16	PCCRL3_A, PCCRL3_D

	write32	CS3BCR_A, CS3BCR_D

	write32	CS3WCR_A, CS3WCR_D

	write32	SDCR_A, SDCR_D

	write32	RTCOR_A, RTCOR_D

	write32	RTCSR_A, RTCSR_D

	/* wait 200us */
	mov.l	REPEAT_D, r3
	mov	#0, r2
repeat0:
	add	#1, r2
	cmp/hs	r3, r2
	bf	repeat0
	nop

	mov.l	SDRAM_MODE, r1
	mov	#0, r0
	mov.l	r0, @r1

	nop
	rts

	.align 4

CCR1_A:		.long CCR1
CCR1_D:		.long 0x0000090B
PCCRL4_A:	.long 0xFFFE3910
PCCRL4_D0:	.long 0x00000000
PECRL4_A:	.long 0xFFFE3A10
PECRL4_D0:	.long 0x00000000
PECRL3_A:	.long 0xFFFE3A12
PECRL3_D:	.long 0x00000000
PEIORL_A:	.long 0xFFFE3A06
PEIORL_D0:	.long 0x00001C00
PEIORL_D1:	.long 0x00001C02
PCIORL_A:	.long 0xFFFE3906
PCIORL_D:	.long 0x00004000
PFCRH2_A:	.long 0xFFFE3A8C
PFCRH2_D:	.long 0x00000000
PFCRH3_A:	.long 0xFFFE3A8A
PFCRH3_D:	.long 0x00000000
PFCRH1_A:	.long 0xFFFE3A8E
PFCRH1_D:	.long 0x00000000
PFIORH_A:	.long 0xFFFE3A84
PFIORH_D:	.long 0x00000729
PECRL1_A:	.long 0xFFFE3A16
PECRL1_D0:	.long 0x00000033


WTCSR_A:	.long 0xFFFE0000
WTCSR_D0:	.long 0x0000A518
WTCSR_D1:	.long 0x0000A51D
WTCNT_A:	.long 0xFFFE0002
WTCNT_D:	.long 0x00005A84
FRQCR_A:	.long 0xFFFE0010
FRQCR_D:	.long 0x00000104

PCCRL4_D1:	.long 0x00000010
PECRL1_D1:	.long 0x00000133

CMNCR_A:	.long 0xFFFC0000
CMNCR_D:	.long 0x00001810
SC0BCR_A:	.long 0xFFFC0004
SC0BCR_D:	.long 0x10000400
CS0WCR_A:	.long 0xFFFC0028
CS0WCR_D:	.long 0x00000B41
PECRL4_D1:	.long 0x00000100
CS1WCR_A:	.long 0xFFFC002C
CS1WCR_D:	.long 0x00000B01
PCCRL4_D2:	.long 0x00000011
PCCRL3_A:	.long 0xFFFE3912
PCCRL3_D:	.long 0x00000011
PCCRL2_A:	.long 0xFFFE3914
PCCRL2_D:	.long 0x00001111
PCCRL1_A:	.long 0xFFFE3916
PCCRL1_D:	.long 0x00001010
PDCRL4_A:	.long 0xFFFE3990
PDCRL4_D:	.long 0x00000011
PDCRL3_A:	.long 0xFFFE3992
PDCRL3_D:	.long 0x00000011
PDCRL2_A:	.long 0xFFFE3994
PDCRL2_D:	.long 0x00001111
PDCRL1_A:	.long 0xFFFE3996
PDCRL1_D:	.long 0x00001000
CS3BCR_A:	.long 0xFFFC0010
CS3BCR_D:	.long 0x00004400
CS3WCR_A:	.long 0xFFFC0034
CS3WCR_D:	.long 0x00002892
SDCR_A:		.long 0xFFFC004C
SDCR_D:		.long 0x00000809
RTCOR_A:	.long 0xFFFC0058
RTCOR_D:	.long 0xA55A0041
RTCSR_A:	.long 0xFFFC0050
RTCSR_D:	.long 0xa55a0010

STBCR3_A:	.long 0xFFFE0408
STBCR3_D:	.long 0x00000000
STBCR4_A:	.long 0xFFFE040C
STBCR4_D:	.long 0x00000008
STBCR5_A:	.long 0xFFFE0410
STBCR5_D:	.long 0x00000000
STBCR6_A:	.long 0xFFFE0414
STBCR6_D:	.long 0x00000002
SDRAM_MODE:	.long 0xFFFC5040
REPEAT_D:	.long 0x00009C40