From 981ee0bd7d280a85d8bab4760b3dfc430b0125c9 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 9 Apr 2019 17:32:46 +0800 Subject: clk: rockchip: rk3399: support pclk_wdt get rate Change-Id: I8634beb815d5129534c36861c2f02e62669889e9 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk_rk3399.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 814f43772e..f11fe3926b 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -252,6 +252,10 @@ enum { DCLK_VOP_DIV_CON_MASK = 0xff, DCLK_VOP_DIV_CON_SHIFT = 0, + /* CLKSEL_CON57 */ + PCLK_ALIVE_DIV_CON_SHIFT = 0, + PCLK_ALIVE_DIV_CON_MASK = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT, + /* CLKSEL_CON58 */ CLK_SPI_PLL_SEL_WIDTH = 1, CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), @@ -1117,6 +1121,17 @@ static ulong rk3399_peri_get_clk(struct rk3399_clk_priv *priv, ulong clk_id) return DIV_TO_RATE(parent, div); } +static ulong rk3399_alive_get_clk(struct rk3399_clk_priv *priv) +{ + struct rk3399_cru *cru = priv->cru; + u32 div, con, parent; + + con = readl(&cru->clksel_con[57]); + div = (con & PCLK_ALIVE_DIV_CON_MASK) >> + PCLK_ALIVE_DIV_CON_SHIFT; + parent = GPLL_HZ; + return DIV_TO_RATE(parent, div); +} #endif static ulong rk3399_clk_get_rate(struct clk *clk) @@ -1184,6 +1199,10 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case PCLK_PERILP1: rate = rk3399_peri_get_clk(priv, clk->id); break; + case PCLK_ALIVE: + case PCLK_WDT: + rate = rk3399_alive_get_clk(priv); + break; #endif default: return -ENOENT; @@ -1620,6 +1639,7 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk) switch (clk->id) { case PCLK_RKPWM_PMU: + case PCLK_WDT_M0_PMU: rate = rk3399_pwm_get_clk(priv->pmucru); break; case SCLK_I2C0_PMU: -- cgit v1.2.3