From 063af872b6421eca3624e8cdd59383d7ea3ac383 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 13 Sep 2019 14:21:04 +0200 Subject: fixup: px30.c - init sdmmc with constants and make emmc boot work --- arch/arm/mach-rockchip/px30/px30.c | 96 ++++++++++++++++++++++++-------------- 1 file changed, 62 insertions(+), 34 deletions(-) diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index e4e25b8a60..8dbd753a62 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -47,19 +47,56 @@ static struct mm_region px30_mem_map[] = { } }; +/* GRF_GPIO1DL_IOMUX */ +enum { + GPIO1D3_SHIFT = 12, + GPIO1D3_MASK = 0xf << GPIO1D3_SHIFT, + GPIO1D3_GPIO = 0, + GPIO1D3_SDMMC_D1, + GPIO1D3_UART2_RXM0, + + GPIO1D2_SHIFT = 8, + GPIO1D2_MASK = 0xf << GPIO1D2_SHIFT, + GPIO1D2_GPIO = 0, + GPIO1D2_SDMMC_D0, + GPIO1D2_UART2_TXM0, +}; + +/* GRF_GPIO1DH_IOMUX */ +enum { + GPIO1D7_SHIFT = 12, + GPIO1D7_MASK = 0xf << GPIO1D7_SHIFT, + GPIO1D7_GPIO = 0, + GPIO1D7_SDMMC_CMD, + + GPIO1D6_SHIFT = 8, + GPIO1D6_MASK = 0xf << GPIO1D6_SHIFT, + GPIO1D6_GPIO = 0, + GPIO1D6_SDMMC_CLK, + + GPIO1D5_SHIFT = 4, + GPIO1D5_MASK = 0xf << GPIO1D5_SHIFT, + GPIO1D5_GPIO = 0, + GPIO1D5_SDMMC_D3, + + GPIO1D4_SHIFT = 0, + GPIO1D4_MASK = 0xf << GPIO1D4_SHIFT, + GPIO1D4_GPIO = 0, + GPIO1D4_SDMMC_D2, +}; + struct mm_region *mem_map = px30_mem_map; #endif #define GRF_BASE 0xff140000 #define CRU_BASE 0xff2b0000 - - -#define GRF_CPU_CON1 0xff140504 +#define DDR_FW_BASE 0xff534000 int arch_cpu_init(void) { static struct px30_grf * const grf = (void *)GRF_BASE; -printf("%s: basic px30 setup\n", __func__); + u32 __maybe_unused val; + #ifdef CONFIG_SPL_BUILD /* We do some SoC one time setting here. */ /* Disable the ddr secure region setting to make it non-secure */ @@ -77,24 +114,30 @@ printf("%s: basic px30 setup\n", __func__); writel(0x05, VIDEO_PHY_BASE + 0x03ac); /* Clear the force_jtag */ - rk_clrreg(GRF_CPU_CON1, 1 << 7); + rk_clrreg(&grf->cpu_con[1], 1 << 7); -/* does not seem to help */ - /* emmc pinmux */ - rk_clrsetreg(GRF_BASE + 0x8, 0xfff0, 0x2220); - rk_clrsetreg(GRF_BASE + 0x0, 0xffff, 0x2222); - rk_clrsetreg(GRF_BASE + 0x4, 0xffff, 0x2222); - - /* emmc pull + drv */ - rk_clrsetreg(GRF_BASE + 0x60, 0xffff, 0x5555); - rk_clrsetreg(GRF_BASE + 0x64, 0x3c, 0x10); - rk_clrsetreg(GRF_BASE + 0xf0, 0xffff, 0xaaaa); - rk_clrsetreg(GRF_BASE + 0xf4, 0x3c, 0x28); +#ifdef CONFIG_SPL_BUILD + /* + * enable master access to dram - undocumented in the manual but + * should set bits [7:0] to 0. + */ + val = readl(DDR_FW_BASE + 0x24); + val &= 0xffffff00; + writel(val, DDR_FW_BASE + 0x24); #if !defined(CONFIG_DEBUG_UART_BOARD_INIT) || CONFIG_DEBUG_UART_BASE != 0xff160000 - /* fix sdmmc pinmux if not used as debug uart */ - rk_clrsetreg(GRF_BASE + 0x18, 0xff00, 0x1100); - rk_clrsetreg(GRF_BASE + 0x1c, 0xffff, 0x1111); + /* fix sdmmc pinmux if not using uart2 as debug uart */ + rk_clrsetreg(&grf->gpio1dl_iomux, + GPIO1D3_MASK | GPIO1D2_MASK, + GPIO1D3_SDMMC_D1 << GPIO1D3_SHIFT | + GPIO1D2_SDMMC_D0 << GPIO1D2_SHIFT); + rk_clrsetreg(&grf->gpio1dh_iomux, + GPIO1D7_MASK | GPIO1D6_MASK | GPIO1D5_MASK | GPIO1D4_MASK, + GPIO1D7_SDMMC_CMD << GPIO1D7_SHIFT | + GPIO1D6_SDMMC_CLK << GPIO1D6_SHIFT | + GPIO1D5_SDMMC_D3 << GPIO1D5_SHIFT | + GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT); +#endif #endif return 0; @@ -159,21 +202,6 @@ void board_debug_uart_init(void) GPIO3A2_UART5_TX << GPIO3A2_SHIFT | GPIO3A1_UART5_RX << GPIO3A1_SHIFT); #else - /* GRF_GPIO1DL_IOMUX */ - enum { - GPIO1D3_SHIFT = 12, - GPIO1D3_MASK = 0xf << GPIO1D3_SHIFT, - GPIO1D3_GPIO = 0, - GPIO1D3_SDMMC_D1, - GPIO1D3_UART2_RXM0, - - GPIO1D2_SHIFT = 8, - GPIO1D2_MASK = 0xf << GPIO1D2_SHIFT, - GPIO1D2_GPIO = 0, - GPIO1D2_SDMMC_D0, - GPIO1D2_UART2_TXM0, - }; - /* GRF_GPIO2BH_IOMUX */ enum { GPIO2B6_SHIFT = 8, -- cgit v1.2.3