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-rw-r--r--drivers/i2c/Makefile2
-rw-r--r--drivers/i2c/adi_i2c.c309
-rw-r--r--drivers/i2c/fti2c010.c340
-rw-r--r--drivers/i2c/fti2c010.h80
-rw-r--r--drivers/mtd/spi/Kconfig1
-rw-r--r--drivers/net/fsl-mc/mc.c39
-rw-r--r--drivers/net/ldpaa_eth/ls1088a.c4
-rw-r--r--drivers/spi/ich.c22
-rw-r--r--drivers/spi/ich.h1
-rw-r--r--drivers/usb/host/Kconfig6
10 files changed, 53 insertions, 751 deletions
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index e7ade94d91..3a8c61b485 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -10,7 +10,6 @@ obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
-obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
@@ -21,7 +20,6 @@ obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
-obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o
diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c
deleted file mode 100644
index d340639e1a..0000000000
--- a/drivers/i2c/adi_i2c.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * i2c.c - driver for ADI TWI/I2C
- *
- * Copyright (c) 2006-2014 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * NOTE: This driver should be converted to driver model before June 2017.
- * Please see doc/driver-model/i2c-howto.txt for instructions.
- */
-
-#include <common.h>
-#include <console.h>
-#include <i2c.h>
-
-#include <asm/clock.h>
-#include <asm/twi.h>
-#include <asm/io.h>
-
-static struct twi_regs *i2c_get_base(struct i2c_adapter *adap);
-
-/* Every register is 32bit aligned, but only 16bits in size */
-#define ureg(name) u16 name; u16 __pad_##name;
-struct twi_regs {
- ureg(clkdiv);
- ureg(control);
- ureg(slave_ctl);
- ureg(slave_stat);
- ureg(slave_addr);
- ureg(master_ctl);
- ureg(master_stat);
- ureg(master_addr);
- ureg(int_stat);
- ureg(int_mask);
- ureg(fifo_ctl);
- ureg(fifo_stat);
- char __pad[0x50];
- ureg(xmt_data8);
- ureg(xmt_data16);
- ureg(rcv_data8);
- ureg(rcv_data16);
-};
-#undef ureg
-
-#ifdef TWI_CLKDIV
-#define TWI0_CLKDIV TWI_CLKDIV
-# ifdef CONFIG_SYS_MAX_I2C_BUS
-# undef CONFIG_SYS_MAX_I2C_BUS
-# endif
-#define CONFIG_SYS_MAX_I2C_BUS 1
-#endif
-
-/*
- * The way speed is changed into duty often results in integer truncation
- * with 50% duty, so we'll force rounding up to the next duty by adding 1
- * to the max. In practice this will get us a speed of something like
- * 385 KHz. The other limit is easy to handle as it is only 8 bits.
- */
-#define I2C_SPEED_MAX 400000
-#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
-#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
-#define I2C_DUTY_MIN 0xff /* 8 bit limited */
-#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
-/* Note: duty is inverse of speed, so the comparisons below are correct */
-#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
-# error "The I2C hardware can only operate 20KHz - 400KHz"
-#endif
-
-/* All transfers are described by this data structure */
-struct adi_i2c_msg {
- u8 flags;
-#define I2C_M_COMBO 0x4
-#define I2C_M_STOP 0x2
-#define I2C_M_READ 0x1
- int len; /* msg length */
- u8 *buf; /* pointer to msg data */
- int alen; /* addr length */
- u8 *abuf; /* addr buffer */
-};
-
-/* Allow msec timeout per ~byte transfer */
-#define I2C_TIMEOUT 10
-
-/**
- * wait_for_completion - manage the actual i2c transfer
- * @msg: the i2c msg
- */
-static int wait_for_completion(struct twi_regs *twi, struct adi_i2c_msg *msg)
-{
- u16 int_stat, ctl;
- ulong timebase = get_timer(0);
-
- do {
- int_stat = readw(&twi->int_stat);
-
- if (int_stat & XMTSERV) {
- writew(XMTSERV, &twi->int_stat);
- if (msg->alen) {
- writew(*(msg->abuf++), &twi->xmt_data8);
- --msg->alen;
- } else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
- writew(*(msg->buf++), &twi->xmt_data8);
- --msg->len;
- } else {
- ctl = readw(&twi->master_ctl);
- if (msg->flags & I2C_M_COMBO)
- writew(ctl | RSTART | MDIR,
- &twi->master_ctl);
- else
- writew(ctl | STOP, &twi->master_ctl);
- }
- }
- if (int_stat & RCVSERV) {
- writew(RCVSERV, &twi->int_stat);
- if (msg->len) {
- *(msg->buf++) = readw(&twi->rcv_data8);
- --msg->len;
- } else if (msg->flags & I2C_M_STOP) {
- ctl = readw(&twi->master_ctl);
- writew(ctl | STOP, &twi->master_ctl);
- }
- }
- if (int_stat & MERR) {
- writew(MERR, &twi->int_stat);
- return msg->len;
- }
- if (int_stat & MCOMP) {
- writew(MCOMP, &twi->int_stat);
- if (msg->flags & I2C_M_COMBO && msg->len) {
- ctl = readw(&twi->master_ctl);
- ctl = (ctl & ~RSTART) |
- (min(msg->len, 0xff) << 6) | MEN | MDIR;
- writew(ctl, &twi->master_ctl);
- } else
- break;
- }
-
- /* If we were able to do something, reset timeout */
- if (int_stat)
- timebase = get_timer(0);
-
- } while (get_timer(timebase) < I2C_TIMEOUT);
-
- return msg->len;
-}
-
-static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr,
- int alen, uint8_t *buffer, int len, uint8_t flags)
-{
- struct twi_regs *twi = i2c_get_base(adap);
- int ret;
- u16 ctl;
- uchar addr_buffer[] = {
- (addr >> 0),
- (addr >> 8),
- (addr >> 16),
- };
- struct adi_i2c_msg msg = {
- .flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
- .buf = buffer,
- .len = len,
- .abuf = addr_buffer,
- .alen = alen,
- };
-
- /* wait for things to settle */
- while (readw(&twi->master_stat) & BUSBUSY)
- if (ctrlc())
- return 1;
-
- /* Set Transmit device address */
- writew(chip, &twi->master_addr);
-
- /* Clear the FIFO before starting things */
- writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl);
- writew(0, &twi->fifo_ctl);
-
- /* prime the pump */
- if (msg.alen) {
- len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
- writew(*(msg.abuf++), &twi->xmt_data8);
- --msg.alen;
- } else if (!(msg.flags & I2C_M_READ) && msg.len) {
- writew(*(msg.buf++), &twi->xmt_data8);
- --msg.len;
- }
-
- /* clear int stat */
- writew(-1, &twi->master_stat);
- writew(-1, &twi->int_stat);
- writew(0, &twi->int_mask);
-
- /* Master enable */
- ctl = readw(&twi->master_ctl);
- ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN |
- ((msg.flags & I2C_M_READ) ? MDIR : 0);
- writew(ctl, &twi->master_ctl);
-
- /* process the rest */
- ret = wait_for_completion(twi, &msg);
-
- if (ret) {
- ctl = readw(&twi->master_ctl) & ~MEN;
- writew(ctl, &twi->master_ctl);
- ctl = readw(&twi->control) & ~TWI_ENA;
- writew(ctl, &twi->control);
- ctl = readw(&twi->control) | TWI_ENA;
- writew(ctl, &twi->control);
- }
-
- return ret;
-}
-
-static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed)
-{
- struct twi_regs *twi = i2c_get_base(adap);
- u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
-
- /* Set TWI interface clock */
- if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
- return -1;
- clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
- writew(clkdiv, &twi->clkdiv);
-
- /* Don't turn it on */
- writew(speed > 100000 ? FAST : 0, &twi->master_ctl);
-
- return 0;
-}
-
-static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
-{
- struct twi_regs *twi = i2c_get_base(adap);
- u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
-
- /* Set TWI internal clock as 10MHz */
- writew(prescale, &twi->control);
-
- /* Set TWI interface clock as specified */
- i2c_set_bus_speed(speed);
-
- /* Enable it */
- writew(TWI_ENA | prescale, &twi->control);
-}
-
-static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip,
- uint addr, int alen, uint8_t *buffer, int len)
-{
- return i2c_transfer(adap, chip, addr, alen, buffer,
- len, alen ? I2C_M_COMBO : I2C_M_READ);
-}
-
-static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip,
- uint addr, int alen, uint8_t *buffer, int len)
-{
- return i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
-}
-
-static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
-{
- u8 byte;
- return adi_i2c_read(adap, chip, 0, 0, &byte, 1);
-}
-
-static struct twi_regs *i2c_get_base(struct i2c_adapter *adap)
-{
- switch (adap->hwadapnr) {
-#if CONFIG_SYS_MAX_I2C_BUS > 2
- case 2:
- return (struct twi_regs *)TWI2_CLKDIV;
-#endif
-#if CONFIG_SYS_MAX_I2C_BUS > 1
- case 1:
- return (struct twi_regs *)TWI1_CLKDIV;
-#endif
- case 0:
- return (struct twi_regs *)TWI0_CLKDIV;
-
- default:
- printf("wrong hwadapnr: %d\n", adap->hwadapnr);
- }
-
- return NULL;
-}
-
-U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe,
- adi_i2c_read, adi_i2c_write,
- adi_i2c_setspeed,
- CONFIG_SYS_I2C_SPEED,
- 0,
- 0)
-
-#if CONFIG_SYS_MAX_I2C_BUS > 1
-U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe,
- adi_i2c_read, adi_i2c_write,
- adi_i2c_setspeed,
- CONFIG_SYS_I2C_SPEED,
- 0,
- 1)
-#endif
-
-#if CONFIG_SYS_MAX_I2C_BUS > 2
-U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe,
- adi_i2c_read, adi_i2c_write,
- adi_i2c_setspeed,
- CONFIG_SYS_I2C_SPEED,
- 0,
- 2)
-#endif
diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c
deleted file mode 100644
index 4da959fa53..0000000000
--- a/drivers/i2c/fti2c010.c
+++ /dev/null
@@ -1,340 +0,0 @@
-/*
- * Faraday I2C Controller
- *
- * (C) Copyright 2010 Faraday Technology
- * Dante Su <dantesu@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * NOTE: This driver should be converted to driver model before June 2017.
- * Please see doc/driver-model/i2c-howto.txt for instructions.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <i2c.h>
-
-#include "fti2c010.h"
-
-#ifndef CONFIG_SYS_I2C_SPEED
-#define CONFIG_SYS_I2C_SPEED 5000
-#endif
-
-#ifndef CONFIG_SYS_I2C_SLAVE
-#define CONFIG_SYS_I2C_SLAVE 0
-#endif
-
-#ifndef CONFIG_FTI2C010_CLOCK
-#define CONFIG_FTI2C010_CLOCK clk_get_rate("I2C")
-#endif
-
-#ifndef CONFIG_FTI2C010_TIMEOUT
-#define CONFIG_FTI2C010_TIMEOUT 10 /* ms */
-#endif
-
-/* 7-bit dev address + 1-bit read/write */
-#define I2C_RD(dev) ((((dev) << 1) & 0xfe) | 1)
-#define I2C_WR(dev) (((dev) << 1) & 0xfe)
-
-struct fti2c010_chip {
- struct fti2c010_regs *regs;
-};
-
-static struct fti2c010_chip chip_list[] = {
- {
- .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE,
- },
-#ifdef CONFIG_FTI2C010_BASE1
- {
- .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE1,
- },
-#endif
-#ifdef CONFIG_FTI2C010_BASE2
- {
- .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE2,
- },
-#endif
-#ifdef CONFIG_FTI2C010_BASE3
- {
- .regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE3,
- },
-#endif
-};
-
-static int fti2c010_reset(struct fti2c010_chip *chip)
-{
- ulong ts;
- int ret = -1;
- struct fti2c010_regs *regs = chip->regs;
-
- writel(CR_I2CRST, &regs->cr);
- for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
- if (!(readl(&regs->cr) & CR_I2CRST)) {
- ret = 0;
- break;
- }
- }
-
- if (ret)
- printf("fti2c010: reset timeout\n");
-
- return ret;
-}
-
-static int fti2c010_wait(struct fti2c010_chip *chip, uint32_t mask)
-{
- int ret = -1;
- uint32_t stat, ts;
- struct fti2c010_regs *regs = chip->regs;
-
- for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
- stat = readl(&regs->sr);
- if ((stat & mask) == mask) {
- ret = 0;
- break;
- }
- }
-
- return ret;
-}
-
-static unsigned int set_i2c_bus_speed(struct fti2c010_chip *chip,
- unsigned int speed)
-{
- struct fti2c010_regs *regs = chip->regs;
- unsigned int clk = CONFIG_FTI2C010_CLOCK;
- unsigned int gsr = 0;
- unsigned int tsr = 32;
- unsigned int div, rate;
-
- for (div = 0; div < 0x3ffff; ++div) {
- /* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
- rate = clk / (2 * (div + 2) + gsr);
- if (rate <= speed)
- break;
- }
-
- writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), &regs->tgsr);
- writel(CDR_DIV(div), &regs->cdr);
-
- return rate;
-}
-
-/*
- * Initialization, must be called once on start up, may be called
- * repeatedly to change the speed and slave addresses.
- */
-static void fti2c010_init(struct i2c_adapter *adap, int speed, int slaveaddr)
-{
- struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
-
- if (adap->init_done)
- return;
-
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
- /* Call board specific i2c bus reset routine before accessing the
- * environment, which might be in a chip on that bus. For details
- * about this problem see doc/I2C_Edge_Conditions.
- */
- i2c_init_board();
-#endif
-
- /* master init */
-
- fti2c010_reset(chip);
-
- set_i2c_bus_speed(chip, speed);
-
- /* slave init, don't care */
-}
-
-/*
- * Probe the given I2C chip address. Returns 0 if a chip responded,
- * not 0 on failure.
- */
-static int fti2c010_probe(struct i2c_adapter *adap, u8 dev)
-{
- struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
- struct fti2c010_regs *regs = chip->regs;
- int ret;
-
- /* 1. Select slave device (7bits Address + 1bit R/W) */
- writel(I2C_WR(dev), &regs->dr);
- writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
- ret = fti2c010_wait(chip, SR_DT);
- if (ret)
- return ret;
-
- /* 2. Select device register */
- writel(0, &regs->dr);
- writel(CR_ENABLE | CR_TBEN, &regs->cr);
- ret = fti2c010_wait(chip, SR_DT);
-
- return ret;
-}
-
-static void to_i2c_addr(u8 *buf, uint32_t addr, int alen)
-{
- int i, shift;
-
- if (!buf || alen <= 0)
- return;
-
- /* MSB first */
- i = 0;
- shift = (alen - 1) * 8;
- while (alen-- > 0) {
- buf[i] = (u8)(addr >> shift);
- shift -= 8;
- }
-}
-
-static int fti2c010_read(struct i2c_adapter *adap,
- u8 dev, uint addr, int alen, uchar *buf, int len)
-{
- struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
- struct fti2c010_regs *regs = chip->regs;
- int ret, pos;
- uchar paddr[4] = { 0 };
-
- to_i2c_addr(paddr, addr, alen);
-
- /*
- * Phase A. Set register address
- */
-
- /* A.1 Select slave device (7bits Address + 1bit R/W) */
- writel(I2C_WR(dev), &regs->dr);
- writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
- ret = fti2c010_wait(chip, SR_DT);
- if (ret)
- return ret;
-
- /* A.2 Select device register */
- for (pos = 0; pos < alen; ++pos) {
- uint32_t ctrl = CR_ENABLE | CR_TBEN;
-
- writel(paddr[pos], &regs->dr);
- writel(ctrl, &regs->cr);
- ret = fti2c010_wait(chip, SR_DT);
- if (ret)
- return ret;
- }
-
- /*
- * Phase B. Get register data
- */
-
- /* B.1 Select slave device (7bits Address + 1bit R/W) */
- writel(I2C_RD(dev), &regs->dr);
- writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
- ret = fti2c010_wait(chip, SR_DT);
- if (ret)
- return ret;
-
- /* B.2 Get register data */
- for (pos = 0; pos < len; ++pos) {
- uint32_t ctrl = CR_ENABLE | CR_TBEN;
- uint32_t stat = SR_DR;
-
- if (pos == len - 1) {
- ctrl |= CR_NAK | CR_STOP;
- stat |= SR_ACK;
- }
- writel(ctrl, &regs->cr);
- ret = fti2c010_wait(chip, stat);
- if (ret)
- break;
- buf[pos] = (uchar)(readl(&regs->dr) & 0xFF);
- }
-
- return ret;
-}
-
-static int fti2c010_write(struct i2c_adapter *adap,
- u8 dev, uint addr, int alen, u8 *buf, int len)
-{
- struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
- struct fti2c010_regs *regs = chip->regs;
- int ret, pos;
- uchar paddr[4] = { 0 };
-
- to_i2c_addr(paddr, addr, alen);
-
- /*
- * Phase A. Set register address
- *
- * A.1 Select slave device (7bits Address + 1bit R/W)
- */
- writel(I2C_WR(dev), &regs->dr);
- writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
- ret = fti2c010_wait(chip, SR_DT);
- if (ret)
- return ret;
-
- /* A.2 Select device register */
- for (pos = 0; pos < alen; ++pos) {
- uint32_t ctrl = CR_ENABLE | CR_TBEN;
-
- writel(paddr[pos], &regs->dr);
- writel(ctrl, &regs->cr);
- ret = fti2c010_wait(chip, SR_DT);
- if (ret)
- return ret;
- }
-
- /*
- * Phase B. Set register data
- */
- for (pos = 0; pos < len; ++pos) {
- uint32_t ctrl = CR_ENABLE | CR_TBEN;
-
- if (pos == len - 1)
- ctrl |= CR_STOP;
- writel(buf[pos], &regs->dr);
- writel(ctrl, &regs->cr);
- ret = fti2c010_wait(chip, SR_DT);
- if (ret)
- break;
- }
-
- return ret;
-}
-
-static unsigned int fti2c010_set_bus_speed(struct i2c_adapter *adap,
- unsigned int speed)
-{
- struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
- int ret;
-
- fti2c010_reset(chip);
- ret = set_i2c_bus_speed(chip, speed);
-
- return ret;
-}
-
-/*
- * Register i2c adapters
- */
-U_BOOT_I2C_ADAP_COMPLETE(i2c_0, fti2c010_init, fti2c010_probe, fti2c010_read,
- fti2c010_write, fti2c010_set_bus_speed,
- CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
- 0)
-#ifdef CONFIG_FTI2C010_BASE1
-U_BOOT_I2C_ADAP_COMPLETE(i2c_1, fti2c010_init, fti2c010_probe, fti2c010_read,
- fti2c010_write, fti2c010_set_bus_speed,
- CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
- 1)
-#endif
-#ifdef CONFIG_FTI2C010_BASE2
-U_BOOT_I2C_ADAP_COMPLETE(i2c_2, fti2c010_init, fti2c010_probe, fti2c010_read,
- fti2c010_write, fti2c010_set_bus_speed,
- CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
- 2)
-#endif
-#ifdef CONFIG_FTI2C010_BASE3
-U_BOOT_I2C_ADAP_COMPLETE(i2c_3, fti2c010_init, fti2c010_probe, fti2c010_read,
- fti2c010_write, fti2c010_set_bus_speed,
- CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
- 3)
-#endif
diff --git a/drivers/i2c/fti2c010.h b/drivers/i2c/fti2c010.h
deleted file mode 100644
index b9d0eb74a6..0000000000
--- a/drivers/i2c/fti2c010.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Faraday I2C Controller
- *
- * (C) Copyright 2010 Faraday Technology
- * Dante Su <dantesu@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __FTI2C010_H
-#define __FTI2C010_H
-
-/*
- * FTI2C010 registers
- */
-struct fti2c010_regs {
- uint32_t cr; /* 0x00: control register */
- uint32_t sr; /* 0x04: status register */
- uint32_t cdr; /* 0x08: clock division register */
- uint32_t dr; /* 0x0c: data register */
- uint32_t sar; /* 0x10: slave address register */
- uint32_t tgsr;/* 0x14: time & glitch suppression register */
- uint32_t bmr; /* 0x18: bus monitor register */
- uint32_t rsvd[5];
- uint32_t revr;/* 0x30: revision register */
-};
-
-/*
- * control register
- */
-#define CR_ALIRQ 0x2000 /* arbitration lost interrupt (master) */
-#define CR_SAMIRQ 0x1000 /* slave address match interrupt (slave) */
-#define CR_STOPIRQ 0x800 /* stop condition interrupt (slave) */
-#define CR_NAKRIRQ 0x400 /* NACK response interrupt (master) */
-#define CR_DRIRQ 0x200 /* rx interrupt (both) */
-#define CR_DTIRQ 0x100 /* tx interrupt (both) */
-#define CR_TBEN 0x80 /* tx enable (both) */
-#define CR_NAK 0x40 /* NACK (both) */
-#define CR_STOP 0x20 /* stop (master) */
-#define CR_START 0x10 /* start (master) */
-#define CR_GCEN 0x8 /* general call support (slave) */
-#define CR_SCLEN 0x4 /* enable clock out (master) */
-#define CR_I2CEN 0x2 /* enable I2C (both) */
-#define CR_I2CRST 0x1 /* reset I2C (both) */
-#define CR_ENABLE \
- (CR_ALIRQ | CR_NAKRIRQ | CR_DRIRQ | CR_DTIRQ | CR_SCLEN | CR_I2CEN)
-
-/*
- * status register
- */
-#define SR_CLRAL 0x400 /* clear arbitration lost */
-#define SR_CLRGC 0x200 /* clear general call */
-#define SR_CLRSAM 0x100 /* clear slave address match */
-#define SR_CLRSTOP 0x80 /* clear stop */
-#define SR_CLRNAKR 0x40 /* clear NACK respond */
-#define SR_DR 0x20 /* rx ready */
-#define SR_DT 0x10 /* tx done */
-#define SR_BB 0x8 /* bus busy */
-#define SR_BUSY 0x4 /* chip busy */
-#define SR_ACK 0x2 /* ACK/NACK received */
-#define SR_RW 0x1 /* set when master-rx or slave-tx mode */
-
-/*
- * clock division register
- */
-#define CDR_DIV(n) ((n) & 0x3ffff)
-
-/*
- * time & glitch suppression register
- */
-#define TGSR_GSR(n) (((n) & 0x7) << 10)
-#define TGSR_TSR(n) ((n) & 0x3ff)
-
-/*
- * bus monitor register
- */
-#define BMR_SCL 0x2 /* SCL is pull-up */
-#define BMR_SDA 0x1 /* SDA is pull-up */
-
-#endif /* __FTI2C010_H */
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 5700859ff2..6ba255d676 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -140,6 +140,7 @@ if SPL
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
+ select SPL_SPI_FLASH_SUPPORT
---help---
Enable support for SPI Flash. This option allows SPL to read from
sunxi SPI Flash. It uses the same method as the boot ROM, so does
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 12dbcd8cc5..be2b6117d7 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -725,9 +725,9 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
* Initialize the global default MC portal
* And check that the MC firmware is responding portal commands:
*/
- root_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
+ root_mc_io = (struct fsl_mc_io *)calloc(sizeof(struct fsl_mc_io), 1);
if (!root_mc_io) {
- printf(" No memory: malloc() failed\n");
+ printf(" No memory: calloc() failed\n");
return -ENOMEM;
}
@@ -879,11 +879,12 @@ static int dpio_init(void)
struct dpio_cfg dpio_cfg;
int err = 0;
- dflt_dpio = (struct fsl_dpio_obj *)malloc(sizeof(struct fsl_dpio_obj));
+ dflt_dpio = (struct fsl_dpio_obj *)calloc(
+ sizeof(struct fsl_dpio_obj), 1);
if (!dflt_dpio) {
- printf("No memory: malloc() failed\n");
+ printf("No memory: calloc() failed\n");
err = -ENOMEM;
- goto err_malloc;
+ goto err_calloc;
}
dpio_cfg.channel_mode = DPIO_LOCAL_CHANNEL;
@@ -948,7 +949,7 @@ err_get_attr:
dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
err_create:
free(dflt_dpio);
-err_malloc:
+err_calloc:
return err;
}
@@ -1030,11 +1031,11 @@ static int dprc_init(void)
goto err_create;
}
- dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
+ dflt_mc_io = (struct fsl_mc_io *)calloc(sizeof(struct fsl_mc_io), 1);
if (!dflt_mc_io) {
err = -ENOMEM;
- printf(" No memory: malloc() failed\n");
- goto err_malloc;
+ printf(" No memory: calloc() failed\n");
+ goto err_calloc;
}
child_portal_id = MC_PORTAL_OFFSET_TO_PORTAL_ID(mc_portal_offset);
@@ -1059,7 +1060,7 @@ static int dprc_init(void)
return 0;
err_child_open:
free(dflt_mc_io);
-err_malloc:
+err_calloc:
dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS,
root_dprc_handle, child_dprc_id);
err_create:
@@ -1110,11 +1111,12 @@ static int dpbp_init(void)
struct dpbp_attr dpbp_attr;
struct dpbp_cfg dpbp_cfg;
- dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj));
+ dflt_dpbp = (struct fsl_dpbp_obj *)calloc(
+ sizeof(struct fsl_dpbp_obj), 1);
if (!dflt_dpbp) {
- printf("No memory: malloc() failed\n");
+ printf("No memory: calloc() failed\n");
err = -ENOMEM;
- goto err_malloc;
+ goto err_calloc;
}
dpbp_cfg.options = 512;
@@ -1164,7 +1166,7 @@ err_get_attr:
dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
err_create:
-err_malloc:
+err_calloc:
return err;
}
@@ -1206,11 +1208,12 @@ static int dpni_init(void)
struct dpni_extended_cfg dpni_extended_cfg;
struct dpni_cfg dpni_cfg;
- dflt_dpni = (struct fsl_dpni_obj *)malloc(sizeof(struct fsl_dpni_obj));
+ dflt_dpni = (struct fsl_dpni_obj *)calloc(
+ sizeof(struct fsl_dpni_obj), 1);
if (!dflt_dpni) {
- printf("No memory: malloc() failed\n");
+ printf("No memory: calloc() failed\n");
err = -ENOMEM;
- goto err_malloc;
+ goto err_calloc;
}
memset(&dpni_extended_cfg, 0, sizeof(dpni_extended_cfg));
@@ -1272,7 +1275,7 @@ err_get_attr:
err_create:
err_prepare_extended_cfg:
free(dflt_dpni);
-err_malloc:
+err_calloc:
return err;
}
diff --git a/drivers/net/ldpaa_eth/ls1088a.c b/drivers/net/ldpaa_eth/ls1088a.c
index 061935e51c..780a23998a 100644
--- a/drivers/net/ldpaa_eth/ls1088a.c
+++ b/drivers/net/ldpaa_eth/ls1088a.c
@@ -99,7 +99,7 @@ void fsl_rgmii_init(void)
ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
if (!ec)
- wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII);
+ wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII_ID);
#endif
#ifdef CONFIG_SYS_FSL_EC2
@@ -108,7 +108,7 @@ void fsl_rgmii_init(void)
ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;
if (!ec)
- wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII);
+ wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII_ID);
#endif
}
#endif
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 22fc83dd72..927bbd708f 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -184,6 +184,19 @@ static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
trans->bytesin -= bytes;
}
+static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
+{
+ if (plat->ich_version == ICHV_7) {
+ struct ich7_spi_regs *ich7_spi = sbase;
+
+ setbits_le16(&ich7_spi->spis, SPIS_LOCK);
+ } else if (plat->ich_version == ICHV_9) {
+ struct ich9_spi_regs *ich9_spi = sbase;
+
+ setbits_le16(&ich9_spi->hsfs, HSFS_FLOCKDN);
+ }
+}
+
static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
{
int lock = 0;
@@ -592,6 +605,12 @@ static int ich_spi_probe(struct udevice *dev)
return ret;
}
+ /* Lock down SPI controller settings if required */
+ if (plat->lockdown) {
+ ich_spi_config_opcode(dev);
+ spi_lock_down(plat, priv->base);
+ }
+
priv->cur_speed = priv->max_speed;
return 0;
@@ -662,6 +681,9 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev)
plat->ich_version = ICHV_9;
}
+ plat->lockdown = fdtdec_get_bool(gd->fdt_blob, node,
+ "intel,spi-lock-down");
+
return ret;
}
diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
index c867c57be9..06b7fb9e01 100644
--- a/drivers/spi/ich.h
+++ b/drivers/spi/ich.h
@@ -174,6 +174,7 @@ enum ich_version {
struct ich_spi_platdata {
enum ich_version ich_version; /* Controller version, 7 or 9 */
+ bool lockdown; /* lock down controller settings? */
};
struct ich_spi_priv {
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index f5f19ed775..5264475fa5 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -71,6 +71,12 @@ config USB_XHCI_DRA7XX_INDEX
Select the DRA7XX xHCI USB index.
Current supported values: 0, 1.
+config USB_XHCI_FSL
+ bool "Support for NXP Layerscape on-chip xHCI USB controller"
+ default y if ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2
+ depends on !SPL_NO_USB
+ help
+ Enables support for the on-chip xHCI controller on NXP Layerscape SoCs.
endif # USB_XHCI_HCD
config USB_EHCI_HCD
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-17 18:58:25 +0000