Merge git://git.denx.de/u-boot-mmc

6 files changed, 485 insertions, 68 deletions

diff --git a/drivers/core/read.c b/drivers/core/read.c
index 065589a6ab..eacf1716fd 100644
--- a/drivers/core/read.c
+++ b/drivers/core/read.c
@@ -81,6 +81,17 @@ int dev_read_stringlist_search(struct udevice *dev, const char *property,
 	return ofnode_stringlist_search(dev_ofnode(dev), property, string);
 }
 
+int dev_read_string_index(struct udevice *dev, const char *propname, int index,
+			  const char **outp)
+{
+	return ofnode_read_string_index(dev_ofnode(dev), propname, index, outp);
+}
+
+int dev_read_string_count(struct udevice *dev, const char *propname)
+{
+	return ofnode_read_string_count(dev_ofnode(dev), propname);
+}
+
 int dev_read_phandle_with_args(struct udevice *dev, const char *list_name,
 				const char *cells_name, int cell_count,
 				int index,
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 6de927b8c6..fa24c52351 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -136,6 +136,7 @@ config MMC_PCI
 config MMC_OMAP_HS
 	bool "TI OMAP High Speed Multimedia Card Interface support"
 	select DM_REGULATOR_PBIAS if DM_MMC && DM_REGULATOR
+	select DM_REGULATOR_PBIAS if DM_MMC && DM_REGULATOR
 	help
 	  This selects the TI OMAP High Speed Multimedia card Interface.
 	  If you have an omap2plus board with a Multimedia Card slot,
@@ -162,12 +163,13 @@ config SH_SDHI
 	  Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform
 
 config MMC_UNIPHIER
-	bool "UniPhier SD/MMC Host Controller support"
-	depends on ARCH_UNIPHIER
+	bool "UniPhier/RCar SD/MMC Host Controller support"
+	depends on ARCH_UNIPHIER || ARCH_RMOBILE
 	depends on BLK && DM_MMC
 	depends on OF_CONTROL
 	help
-	  This selects support for the SD/MMC Host Controller on UniPhier SoCs.
+	  This selects support for the Matsushita SD/MMC Host Controller on
+	  SocioNext UniPhier and Renesas RCar SoCs.
 
 config MMC_SANDBOX
 	bool "Sandbox MMC support"
diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index 721b75fdda..0786ad0d5f 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -132,8 +132,43 @@ struct uniphier_sd_priv {
 #define UNIPHIER_SD_CAP_NONREMOVABLE	BIT(0)	/* Nonremovable e.g. eMMC */
 #define UNIPHIER_SD_CAP_DMA_INTERNAL	BIT(1)	/* have internal DMA engine */
 #define UNIPHIER_SD_CAP_DIV1024		BIT(2)	/* divisor 1024 is available */
+#define UNIPHIER_SD_CAP_64BIT		BIT(3)	/* Controller is 64bit */
 };
 
+static u64 uniphier_sd_readq(struct uniphier_sd_priv *priv, const u32 reg)
+{
+	if (priv->caps & UNIPHIER_SD_CAP_64BIT)
+		return readq(priv->regbase + (reg << 1));
+	else
+		return readq(priv->regbase + reg);
+}
+
+static void uniphier_sd_writeq(struct uniphier_sd_priv *priv,
+			       const u64 val, const u32 reg)
+{
+	if (priv->caps & UNIPHIER_SD_CAP_64BIT)
+		writeq(val, priv->regbase + (reg << 1));
+	else
+		writeq(val, priv->regbase + reg);
+}
+
+static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, const u32 reg)
+{
+	if (priv->caps & UNIPHIER_SD_CAP_64BIT)
+		return readl(priv->regbase + (reg << 1));
+	else
+		return readl(priv->regbase + reg);
+}
+
+static void uniphier_sd_writel(struct uniphier_sd_priv *priv,
+			       const u32 val, const u32 reg)
+{
+	if (priv->caps & UNIPHIER_SD_CAP_64BIT)
+		writel(val, priv->regbase + (reg << 1));
+	else
+		writel(val, priv->regbase + reg);
+}
+
 static dma_addr_t __dma_map_single(void *ptr, size_t size,
 				   enum dma_data_direction dir)
 {
@@ -157,7 +192,7 @@ static void __dma_unmap_single(dma_addr_t addr, size_t size,
 static int uniphier_sd_check_error(struct udevice *dev)
 {
 	struct uniphier_sd_priv *priv = dev_get_priv(dev);
-	u32 info2 = readl(priv->regbase + UNIPHIER_SD_INFO2);
+	u32 info2 = uniphier_sd_readl(priv, UNIPHIER_SD_INFO2);
 
 	if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) {
 		/*
@@ -195,7 +230,7 @@ static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
 	long wait = 1000000;
 	int ret;
 
-	while (!(readl(priv->regbase + reg) & flag)) {
+	while (!(uniphier_sd_readl(priv, reg) & flag)) {
 		if (wait-- < 0) {
 			dev_err(dev, "timeout\n");
 			return -ETIMEDOUT;
@@ -227,15 +262,40 @@ static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf,
 	 * Clear the status flag _before_ read the buffer out because
 	 * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered.
 	 */
-	writel(0, priv->regbase + UNIPHIER_SD_INFO2);
+	uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
 
 	if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
-		for (i = 0; i < blocksize / 4; i++)
-			*(*pbuf)++ = readl(priv->regbase + UNIPHIER_SD_BUF);
+		if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
+			for (i = 0; i < blocksize / 8; i++) {
+				u64 data;
+				data = uniphier_sd_readq(priv,
+							 UNIPHIER_SD_BUF);
+				*(*pbuf)++ = data;
+				*(*pbuf)++ = data >> 32;
+			}
+		} else {
+			for (i = 0; i < blocksize / 4; i++) {
+				u32 data;
+				data = uniphier_sd_readl(priv, UNIPHIER_SD_BUF);
+				*(*pbuf)++ = data;
+			}
+		}
 	} else {
-		for (i = 0; i < blocksize / 4; i++)
-			put_unaligned(readl(priv->regbase + UNIPHIER_SD_BUF),
-				      (*pbuf)++);
+		if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
+			for (i = 0; i < blocksize / 8; i++) {
+				u64 data;
+				data = uniphier_sd_readq(priv,
+							 UNIPHIER_SD_BUF);
+				put_unaligned(data, (*pbuf)++);
+				put_unaligned(data >> 32, (*pbuf)++);
+			}
+		} else {
+			for (i = 0; i < blocksize / 4; i++) {
+				u32 data;
+				data = uniphier_sd_readl(priv, UNIPHIER_SD_BUF);
+				put_unaligned(data, (*pbuf)++);
+			}
+		}
 	}
 
 	return 0;
@@ -253,15 +313,37 @@ static int uniphier_sd_pio_write_one_block(struct udevice *dev,
 	if (ret)
 		return ret;
 
-	writel(0, priv->regbase + UNIPHIER_SD_INFO2);
+	uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
 
 	if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
-		for (i = 0; i < blocksize / 4; i++)
-			writel(*(*pbuf)++, priv->regbase + UNIPHIER_SD_BUF);
+		if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
+			for (i = 0; i < blocksize / 8; i++) {
+				u64 data = *(*pbuf)++;
+				data |= (u64)*(*pbuf)++ << 32;
+				uniphier_sd_writeq(priv, data,
+						   UNIPHIER_SD_BUF);
+			}
+		} else {
+			for (i = 0; i < blocksize / 4; i++) {
+				uniphier_sd_writel(priv, *(*pbuf)++,
+						   UNIPHIER_SD_BUF);
+			}
+		}
 	} else {
-		for (i = 0; i < blocksize / 4; i++)
-			writel(get_unaligned((*pbuf)++),
-			       priv->regbase + UNIPHIER_SD_BUF);
+		if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
+			for (i = 0; i < blocksize / 8; i++) {
+				u64 data = get_unaligned((*pbuf)++);
+				data |= (u64)get_unaligned((*pbuf)++) << 32;
+				uniphier_sd_writeq(priv, data,
+						   UNIPHIER_SD_BUF);
+			}
+		} else {
+			for (i = 0; i < blocksize / 4; i++) {
+				u32 data = get_unaligned((*pbuf)++);
+				uniphier_sd_writel(priv, data,
+						   UNIPHIER_SD_BUF);
+			}
+		}
 	}
 
 	return 0;
@@ -292,22 +374,22 @@ static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv,
 {
 	u32 tmp;
 
-	writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO1);
-	writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO2);
+	uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO1);
+	uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO2);
 
 	/* enable DMA */
-	tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE);
+	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE);
 	tmp |= UNIPHIER_SD_EXTMODE_DMA_EN;
-	writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE);
 
-	writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_L);
+	uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_L);
 
 	/* suppress the warning "right shift count >= width of type" */
 	dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
 
-	writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_H);
+	uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_H);
 
-	writel(UNIPHIER_SD_DMA_CTL_START, priv->regbase + UNIPHIER_SD_DMA_CTL);
+	uniphier_sd_writel(priv, UNIPHIER_SD_DMA_CTL_START, UNIPHIER_SD_DMA_CTL);
 }
 
 static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
@@ -316,7 +398,7 @@ static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
 	struct uniphier_sd_priv *priv = dev_get_priv(dev);
 	long wait = 1000000 + 10 * blocks;
 
-	while (!(readl(priv->regbase + UNIPHIER_SD_DMA_INFO1) & flag)) {
+	while (!(uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO1) & flag)) {
 		if (wait-- < 0) {
 			dev_err(dev, "timeout during DMA\n");
 			return -ETIMEDOUT;
@@ -325,7 +407,7 @@ static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
 		udelay(10);
 	}
 
-	if (readl(priv->regbase + UNIPHIER_SD_DMA_INFO2)) {
+	if (uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO2)) {
 		dev_err(dev, "error during DMA\n");
 		return -EIO;
 	}
@@ -343,7 +425,7 @@ static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
 	u32 poll_flag, tmp;
 	int ret;
 
-	tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE);
+	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE);
 
 	if (data->flags & MMC_DATA_READ) {
 		buf = data->dest;
@@ -357,7 +439,7 @@ static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
 		tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD;
 	}
 
-	writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE);
 
 	dma_addr = __dma_map_single(buf, len, dir);
 
@@ -396,27 +478,27 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 	int ret;
 	u32 tmp;
 
-	if (readl(priv->regbase + UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) {
+	if (uniphier_sd_readl(priv, UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) {
 		dev_err(dev, "command busy\n");
 		return -EBUSY;
 	}
 
 	/* clear all status flags */
-	writel(0, priv->regbase + UNIPHIER_SD_INFO1);
-	writel(0, priv->regbase + UNIPHIER_SD_INFO2);
+	uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO1);
+	uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
 
 	/* disable DMA once */
-	tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE);
+	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE);
 	tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN;
-	writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE);
 
-	writel(cmd->cmdarg, priv->regbase + UNIPHIER_SD_ARG);
+	uniphier_sd_writel(priv, cmd->cmdarg, UNIPHIER_SD_ARG);
 
 	tmp = cmd->cmdidx;
 
 	if (data) {
-		writel(data->blocksize, priv->regbase + UNIPHIER_SD_SIZE);
-		writel(data->blocks, priv->regbase + UNIPHIER_SD_SECCNT);
+		uniphier_sd_writel(priv, data->blocksize, UNIPHIER_SD_SIZE);
+		uniphier_sd_writel(priv, data->blocks, UNIPHIER_SD_SECCNT);
 
 		/* Do not send CMD12 automatically */
 		tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA;
@@ -457,7 +539,7 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 
 	dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
 		cmd->cmdidx, tmp, cmd->cmdarg);
-	writel(tmp, priv->regbase + UNIPHIER_SD_CMD);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CMD);
 
 	ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
 				       UNIPHIER_SD_INFO1_RSP);
@@ -465,10 +547,10 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 		return ret;
 
 	if (cmd->resp_type & MMC_RSP_136) {
-		u32 rsp_127_104 = readl(priv->regbase + UNIPHIER_SD_RSP76);
-		u32 rsp_103_72 = readl(priv->regbase + UNIPHIER_SD_RSP54);
-		u32 rsp_71_40 = readl(priv->regbase + UNIPHIER_SD_RSP32);
-		u32 rsp_39_8 = readl(priv->regbase + UNIPHIER_SD_RSP10);
+		u32 rsp_127_104 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP76);
+		u32 rsp_103_72 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP54);
+		u32 rsp_71_40 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP32);
+		u32 rsp_39_8 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10);
 
 		cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
 				   ((rsp_103_72  & 0xff000000) >> 24);
@@ -479,7 +561,7 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 		cmd->response[3] = (rsp_39_8     & 0xffffff)   << 8;
 	} else {
 		/* bit 39-8 */
-		cmd->response[0] = readl(priv->regbase + UNIPHIER_SD_RSP10);
+		cmd->response[0] = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10);
 	}
 
 	if (data) {
@@ -518,10 +600,10 @@ static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv,
 		return -EINVAL;
 	}
 
-	tmp = readl(priv->regbase + UNIPHIER_SD_OPTION);
+	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_OPTION);
 	tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK;
 	tmp |= val;
-	writel(tmp, priv->regbase + UNIPHIER_SD_OPTION);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_OPTION);
 
 	return 0;
 }
@@ -531,12 +613,12 @@ static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv,
 {
 	u32 tmp;
 
-	tmp = readl(priv->regbase + UNIPHIER_SD_IF_MODE);
+	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_IF_MODE);
 	if (mmc->ddr_mode)
 		tmp |= UNIPHIER_SD_IF_MODE_DDR;
 	else
 		tmp &= ~UNIPHIER_SD_IF_MODE_DDR;
-	writel(tmp, priv->regbase + UNIPHIER_SD_IF_MODE);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_IF_MODE);
 }
 
 static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv,
@@ -573,21 +655,21 @@ static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv,
 	else
 		val = UNIPHIER_SD_CLKCTL_DIV1024;
 
-	tmp = readl(priv->regbase + UNIPHIER_SD_CLKCTL);
+	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL);
 	if (tmp & UNIPHIER_SD_CLKCTL_SCLKEN &&
 	    (tmp & UNIPHIER_SD_CLKCTL_DIV_MASK) == val)
 		return;
 
 	/* stop the clock before changing its rate to avoid a glitch signal */
 	tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN;
-	writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
 
 	tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK;
 	tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN;
-	writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
 
 	tmp |= UNIPHIER_SD_CLKCTL_SCLKEN;
-	writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
 
 	udelay(1000);
 }
@@ -617,7 +699,7 @@ static int uniphier_sd_get_cd(struct udevice *dev)
 	if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE)
 		return 1;
 
-	return !!(readl(priv->regbase + UNIPHIER_SD_INFO1) &
+	return !!(uniphier_sd_readl(priv, UNIPHIER_SD_INFO1) &
 		  UNIPHIER_SD_INFO1_CD);
 }
 
@@ -632,28 +714,28 @@ static void uniphier_sd_host_init(struct uniphier_sd_priv *priv)
 	u32 tmp;
 
 	/* soft reset of the host */
-	tmp = readl(priv->regbase + UNIPHIER_SD_SOFT_RST);
+	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_SOFT_RST);
 	tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX;
-	writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST);
 	tmp |= UNIPHIER_SD_SOFT_RST_RSTX;
-	writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST);
 
 	/* FIXME: implement eMMC hw_reset */
 
-	writel(UNIPHIER_SD_STOP_SEC, priv->regbase + UNIPHIER_SD_STOP);
+	uniphier_sd_writel(priv, UNIPHIER_SD_STOP_SEC, UNIPHIER_SD_STOP);
 
 	/*
 	 * Connected to 32bit AXI.
 	 * This register dropped backward compatibility at version 0x10.
 	 * Write an appropriate value depending on the IP version.
 	 */
-	writel(priv->version >= 0x10 ? 0x00000101 : 0x00000000,
-	       priv->regbase + UNIPHIER_SD_HOST_MODE);
+	uniphier_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000,
+			   UNIPHIER_SD_HOST_MODE);
 
 	if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) {
-		tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE);
+		tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE);
 		tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
-		writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE);
+		uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE);
 	}
 }
 
@@ -669,6 +751,7 @@ static int uniphier_sd_probe(struct udevice *dev)
 	struct uniphier_sd_plat *plat = dev_get_platdata(dev);
 	struct uniphier_sd_priv *priv = dev_get_priv(dev);
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+	const u32 quirks = dev_get_driver_data(dev);
 	fdt_addr_t base;
 	struct clk clk;
 	int ret;
@@ -720,18 +803,22 @@ static int uniphier_sd_probe(struct udevice *dev)
 		return -EINVAL;
 	}
 
+	if (quirks) {
+		priv->caps = quirks;
+	} else {
+		priv->version = uniphier_sd_readl(priv, UNIPHIER_SD_VERSION) &
+							UNIPHIER_SD_VERSION_IP;
+		dev_dbg(dev, "version %x\n", priv->version);
+		if (priv->version >= 0x10) {
+			priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL;
+			priv->caps |= UNIPHIER_SD_CAP_DIV1024;
+		}
+	}
+
 	if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
 			     NULL))
 		priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE;
 
-	priv->version = readl(priv->regbase + UNIPHIER_SD_VERSION) &
-							UNIPHIER_SD_VERSION_IP;
-	dev_dbg(dev, "version %x\n", priv->version);
-	if (priv->version >= 0x10) {
-		priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL;
-		priv->caps |= UNIPHIER_SD_CAP_DIV1024;
-	}
-
 	uniphier_sd_host_init(priv);
 
 	plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
@@ -746,7 +833,9 @@ static int uniphier_sd_probe(struct udevice *dev)
 }
 
 static const struct udevice_id uniphier_sd_match[] = {
-	{ .compatible = "socionext,uniphier-sdhc" },
+	{ .compatible = "renesas,sdhi-r8a7795", .data = UNIPHIER_SD_CAP_64BIT },
+	{ .compatible = "renesas,sdhi-r8a7796", .data = UNIPHIER_SD_CAP_64BIT },
+	{ .compatible = "socionext,uniphier-sdhc", .data = 0 },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index c82a936e8a..2cfade1cb2 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -151,6 +151,19 @@ config DM_REGULATOR_PALMAS
 	features for REGULATOR PALMAS and the family of PALMAS PMICs.
 	The driver implements get/set api for: value and enable.
 
+config DM_REGULATOR_PBIAS
+	bool "Enable driver for PBIAS regulator"
+	depends on DM_REGULATOR
+	select REGMAP
+	select SYSCON
+	---help---
+	This enables implementation of driver-model regulator uclass
+	features for pseudo-regulator PBIAS found in the OMAP SOCs.
+	This pseudo-regulator is used to provide a BIAS voltage to MMC1
+	signal pads and must be configured properly during a voltage switch.
+	Voltage switching is required by some operating modes of SDcards and
+	eMMC.
+
 config DM_REGULATOR_LP873X
 	bool "Enable driver for LP873X PMIC regulators"
         depends on PMIC_LP873X
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 18fb870e43..6c149a9263 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
 obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
 obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_PBIAS) += pbias_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o
diff --git a/drivers/power/regulator/pbias_regulator.c b/drivers/power/regulator/pbias_regulator.c
new file mode 100644
index 0000000000..914500b729
--- /dev/null
+++ b/drivers/power/regulator/pbias_regulator.c
@@ -0,0 +1,301 @@
+/*
+ * (C) Copyright 2016 Texas Instruments Incorporated, <www.ti.com>
+ * Jean-Jacques Hiblot <jjhiblot@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+#include <linux/ioport.h>
+#include <dm/read.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pbias_reg_info {
+	u32 enable;
+	u32 enable_mask;
+	u32 disable_val;
+	u32 vmode;
+	unsigned int enable_time;
+	char *name;
+};
+
+struct pbias_priv {
+	struct regmap *regmap;
+	int offset;
+};
+
+static const struct pmic_child_info pmic_children_info[] = {
+	{ .prefix = "pbias", .driver = "pbias_regulator"},
+	{ },
+};
+
+static int pbias_write(struct udevice *dev, uint reg, const uint8_t *buff,
+		       int len)
+{
+	struct pbias_priv *priv = dev_get_priv(dev);
+	u32 val = *(u32 *)buff;
+
+	if (len != 4)
+		return -EINVAL;
+
+	return regmap_write(priv->regmap, priv->offset, val);
+}
+
+static int pbias_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+	struct pbias_priv *priv = dev_get_priv(dev);
+
+	if (len != 4)
+		return -EINVAL;
+
+	return regmap_read(priv->regmap, priv->offset, (u32 *)buff);
+}
+
+static int pbias_ofdata_to_platdata(struct udevice *dev)
+{
+	struct pbias_priv *priv = dev_get_priv(dev);
+	struct udevice *syscon;
+	struct regmap *regmap;
+	struct resource res;
+	int err;
+
+	err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+					   "syscon", &syscon);
+	if (err) {
+		error("%s: unable to find syscon device (%d)\n", __func__,
+		      err);
+		return err;
+	}
+
+	regmap = syscon_get_regmap(syscon);
+	if (IS_ERR(regmap)) {
+		error("%s: unable to find regmap (%ld)\n", __func__,
+		      PTR_ERR(regmap));
+		return PTR_ERR(regmap);
+	}
+	priv->regmap = regmap;
+
+	err = dev_read_resource(dev, 0, &res);
+	if (err) {
+		error("%s: unable to find offset (%d)\n", __func__, err);
+		return err;
+	}
+	priv->offset = res.start;
+
+	return 0;
+}
+
+static int pbias_bind(struct udevice *dev)
+{
+	int children;
+
+	children = pmic_bind_children(dev, dev->node, pmic_children_info);
+	if (!children)
+		debug("%s: %s - no child found\n", __func__, dev->name);
+
+	return 0;
+}
+
+static struct dm_pmic_ops pbias_ops = {
+	.read = pbias_read,
+	.write = pbias_write,
+};
+
+static const struct udevice_id pbias_ids[] = {
+	{ .compatible = "ti,pbias-dra7" },
+	{ }
+};
+
+U_BOOT_DRIVER(pbias_pmic) = {
+	.name = "pbias_pmic",
+	.id = UCLASS_PMIC,
+	.of_match = pbias_ids,
+	.bind = pbias_bind,
+	.ops = &pbias_ops,
+	.ofdata_to_platdata = pbias_ofdata_to_platdata,
+	.priv_auto_alloc_size = sizeof(struct pbias_priv),
+};
+
+static const struct pbias_reg_info pbias_mmc_omap2430 = {
+	.enable = BIT(1),
+	.enable_mask = BIT(1),
+	.vmode = BIT(0),
+	.disable_val = 0,
+	.enable_time = 100,
+	.name = "pbias_mmc_omap2430"
+};
+
+static const struct pbias_reg_info pbias_sim_omap3 = {
+	.enable = BIT(9),
+	.enable_mask = BIT(9),
+	.vmode = BIT(8),
+	.enable_time = 100,
+	.name = "pbias_sim_omap3"
+};
+
+static const struct pbias_reg_info pbias_mmc_omap4 = {
+	.enable = BIT(26) | BIT(22),
+	.enable_mask = BIT(26) | BIT(25) | BIT(22),
+	.disable_val = BIT(25),
+	.vmode = BIT(21),
+	.enable_time = 100,
+	.name = "pbias_mmc_omap4"
+};
+
+static const struct pbias_reg_info pbias_mmc_omap5 = {
+	.enable = BIT(27) | BIT(26),
+	.enable_mask = BIT(27) | BIT(25) | BIT(26),
+	.disable_val = BIT(25),
+	.vmode = BIT(21),
+	.enable_time = 100,
+	.name = "pbias_mmc_omap5"
+};
+
+static const struct pbias_reg_info *pbias_reg_infos[] = {
+	&pbias_mmc_omap5,
+	&pbias_mmc_omap4,
+	&pbias_sim_omap3,
+	&pbias_mmc_omap2430,
+	NULL
+};
+
+static int pbias_regulator_probe(struct udevice *dev)
+{
+	const struct pbias_reg_info **p = pbias_reg_infos;
+	struct dm_regulator_uclass_platdata *uc_pdata;
+
+	uc_pdata = dev_get_uclass_platdata(dev);
+
+	while (*p) {
+		int rc;
+
+		rc = dev_read_stringlist_search(dev, "regulator-name",
+						(*p)->name);
+		if (rc >= 0) {
+			debug("found regulator %s\n", (*p)->name);
+			break;
+		} else if (rc != -ENODATA) {
+			return rc;
+		}
+		p++;
+	}
+	if (!*p) {
+		int i = 0;
+		const char *s;
+
+		debug("regulator ");
+		while (dev_read_string_index(dev, "regulator-name", i++, &s) >= 0)
+			debug("%s'%s' ", (i > 1) ? ", " : "", s);
+		debug("%s not supported\n", (i > 2) ? "are" : "is");
+		return -EINVAL;
+	}
+
+	uc_pdata->type = REGULATOR_TYPE_OTHER;
+	dev->priv = (void *)*p;
+
+	return 0;
+}
+
+static int pbias_regulator_get_value(struct udevice *dev)
+{
+	const struct pbias_reg_info *p = dev_get_priv(dev);
+	int rc;
+	u32 reg;
+
+	rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
+	if (rc)
+		return rc;
+
+	debug("%s voltage id %s\n", p->name,
+	      (reg & p->vmode) ? "3.0v" : "1.8v");
+	return (reg & p->vmode) ? 3000000 : 1800000;
+}
+
+static int pbias_regulator_set_value(struct udevice *dev, int uV)
+{
+	const struct pbias_reg_info *p = dev_get_priv(dev);
+	int rc;
+	u32 reg;
+
+	debug("Setting %s voltage to %s\n", p->name,
+	      (reg & p->vmode) ? "3.0v" : "1.8v");
+
+	rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
+	if (rc)
+		return rc;
+
+	if (uV == 3000000)
+		reg |= p->vmode;
+	else if (uV == 1800000)
+		reg &= ~p->vmode;
+	else
+		return -EINVAL;
+
+	return pmic_write(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
+}
+
+static int pbias_regulator_get_enable(struct udevice *dev)
+{
+	const struct pbias_reg_info *p = dev_get_priv(dev);
+	int rc;
+	u32 reg;
+
+	rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
+	if (rc)
+		return rc;
+
+	debug("%s id %s\n", p->name,
+	      (reg & p->enable_mask) == (p->disable_val) ? "on" : "off");
+
+	return (reg & p->enable_mask) == (p->disable_val);
+}
+
+static int pbias_regulator_set_enable(struct udevice *dev, bool enable)
+{
+	const struct pbias_reg_info *p = dev_get_priv(dev);
+	int rc;
+	u32 reg;
+
+	debug("Turning %s %s\n", enable ? "on" : "off", p->name);
+
+	rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
+	if (rc)
+		return rc;
+
+	reg &= ~p->enable_mask;
+	if (enable)
+		reg |= p->enable;
+	else
+		reg |= p->disable_val;
+
+	rc = pmic_write(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
+	if (rc)
+		return rc;
+
+	if (enable)
+		udelay(p->enable_time);
+
+	return 0;
+}
+
+static const struct dm_regulator_ops pbias_regulator_ops = {
+	.get_value  = pbias_regulator_get_value,
+	.set_value  = pbias_regulator_set_value,
+	.get_enable = pbias_regulator_get_enable,
+	.set_enable = pbias_regulator_set_enable,
+};
+
+U_BOOT_DRIVER(pbias_regulator) = {
+	.name = "pbias_regulator",
+	.id = UCLASS_REGULATOR,
+	.ops = &pbias_regulator_ops,
+	.probe = pbias_regulator_probe,
+};