diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2018-06-12 01:26:47 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2018-06-13 09:50:57 +0800 |
| commit | bee053e248e93d82e5c352708f8c892f4a488c54 (patch) | |
| tree | 8afb5efcb8ab0bf9fec1bd9658a9faeea894547f /configs/cougarcanyon2_defconfig | |
| parent | 51050ff0a239f2640467d4c2fe54e0e8679a4093 (diff) | |
x86: cougarcanyon2: Add missing chipset interrupt information
Add Panther Point chipset interrupt pin/PIRQ information, and
enable the generation of PIRQ routing table and MP table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'configs/cougarcanyon2_defconfig')
| -rw-r--r-- | configs/cougarcanyon2_defconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 98d9aa0f3a..eeee2521c6 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -6,6 +6,8 @@ CONFIG_TARGET_COUGARCANYON2=y # CONFIG_HAVE_INTEL_ME is not set # CONFIG_ENABLE_MRC_CACHE is not set CONFIG_SMP=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y |