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authorKever Yang <kever.yang@rock-chips.com>2019-07-22 20:02:11 +0800
committerKever Yang <kever.yang@rock-chips.com>2019-07-29 10:26:41 +0800
commit0221910042a629e3439576e8807f04b612c94fd5 (patch)
tree957c5fb6c0af6d39babbc923a5b8c2cb6eadc75a /board
parent1e7d2be011c2f51e62d3096a7bd808f9d4feb2ca (diff)
rockchip: rk3288: move board_early_init_f() back to veyron
The board_early_init_f() is only used by veyron board now, move it into the board file veyron.c Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'board')
-rw-r--r--board/google/veyron/veyron.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c
index 19edb18a66..361f0e9da2 100644
--- a/board/google/veyron/veyron.c
+++ b/board/google/veyron/veyron.c
@@ -4,9 +4,29 @@
*/
#include <common.h>
+#include <asm/arch-rockchip/clock.h>
/*
* We should increase the DDR voltage to 1.2V using the PWM regulator.
* There is a U-Boot driver for this but it may need to add support for the
* 'voltage-table' property.
*/
+
+int board_early_init_f(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ /*
+ * This init is done in SPL, but when chain-loading U-Boot SPL will
+ * have been skipped. Allow the clock driver to check if it needs
+ * setting up.
+ */
+ ret = rockchip_get_clk(&dev);
+ if (ret) {
+ debug("CLK init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}