diff options
| author | Tom Rini <trini@konsulko.com> | 2019-02-28 18:57:32 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-02-28 18:57:32 -0500 |
| commit | cfba74d0bef350d81241b059180bcc5a1e93bdfa (patch) | |
| tree | 125d54fbb44b958899ed63c9880f546d0f75dd5b /arch | |
| parent | 35b05146f6a4853554b18ddc196d3bfcab5dd734 (diff) | |
| parent | 4a9743f73c10a4b3801be3b662a892f61617256e (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- SoCFPGA cache/gpio fixes
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-socfpga/misc.c | 3 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/spl_gen5.c | 58 |
2 files changed, 61 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index e1adea143c..fcf211d62b 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -62,6 +62,9 @@ void v7_outer_cache_enable(void) /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + writel(0x111, &pl310->pl310_tag_latency_ctrl); + writel(0x121, &pl310->pl310_data_latency_ctrl); + /* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 4c9f7997be..142b60f887 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -5,6 +5,7 @@ #include <common.h> #include <asm/io.h> +#include <asm/pl310.h> #include <asm/u-boot.h> #include <asm/utils.h> #include <image.h> @@ -23,6 +24,8 @@ DECLARE_GLOBAL_DATA_PTR; +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static const struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; @@ -63,6 +66,60 @@ u32 spl_boot_mode(const u32 boot_device) } #endif +static void socfpga_pl310_clear(void) +{ + u32 mask = 0xff, ena = 0; + + icache_enable(); + + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + + writel(0x111, &pl310->pl310_tag_latency_ctrl); + writel(0x121, &pl310->pl310_data_latency_ctrl); + + /* enable BRESP, instruction and data prefetch, full line of zeroes */ + setbits_le32(&pl310->pl310_aux_ctrl, + L310_AUX_CTRL_DATA_PREFETCH_MASK | + L310_AUX_CTRL_INST_PREFETCH_MASK | + L310_SHARED_ATT_OVERRIDE_ENABLE); + + /* Enable the L2 cache */ + ena = readl(&pl310->pl310_ctrl); + ena |= L2X0_CTRL_EN; + + /* + * Invalidate the PL310 L2 cache. Keep the invalidation code + * entirely in L1 I-cache to avoid any bus traffic through + * the L2. + */ + asm volatile( + ".align 5 \n" + " b 3f \n" + "1: str %1, [%4] \n" + " dsb \n" + " isb \n" + " str %0, [%2] \n" + " dsb \n" + " isb \n" + "2: ldr %0, [%2] \n" + " cmp %0, #0 \n" + " bne 2b \n" + " str %0, [%3] \n" + " dsb \n" + " isb \n" + " b 4f \n" + "3: b 1b \n" + "4: nop \n" + : "+r"(mask), "+r"(ena) + : "r"(&pl310->pl310_inv_way), + "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) + : "memory", "cc"); + + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); @@ -85,6 +142,7 @@ void board_init_f(ulong dummy) memset(__bss_start, 0, __bss_end - __bss_start); socfpga_sdram_remap_zero(); + socfpga_pl310_clear(); debug("Freezing all I/O banks\n"); /* freeze all IO banks */ |