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authorPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>2017-05-31 18:50:38 +0800
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>2017-11-01 23:20:53 +0100
commit987a4529d1e23400fe632aa68fe3a75e31b2b0b2 (patch)
treeeacdd2fabe58ba24e2029e5fadb72facb585d7ab
parentf784a6a93be8fdb0866bde3d81ea735316bbb6d8 (diff)
rockchip: enable boot0-hook for all Rockchip SoCs
Rockchip SoCs bootrom design is like this: - First 2KB or 4KB internal memory is for bootrom stack and heap; - Then the first 4-byte suppose to be a TAG like 'RK33'; - The the following memory address end with '0004' is the first instruction load and running by bootrom; Let's use the boot0 hook to reserve the first 4-byte tag for all the Rockchip SoCs. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems> [Commit message:] Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-rockchip/Kconfig2
2 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 83b7aa51dc..3bee75f2bc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1118,6 +1118,7 @@ config ARCH_ROCKCHIP
select DM_USB if USB
select DM_PWM
select DM_REGULATOR
+ select ENABLE_ARM_SOC_BOOT0_HOOK
imply CMD_FASTBOOT
imply FASTBOOT
imply FAT_WRITE
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index d9b25d5de4..31e9864c8d 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -74,7 +74,6 @@ config ROCKCHIP_RK3368
imply SPL_SEPARATE_BSS
imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT
- select ENABLE_ARM_SOC_BOOT0_HOOK
select DEBUG_UART_BOARD_INIT
select SYS_NS16550
help
@@ -112,7 +111,6 @@ config ROCKCHIP_RK3399
select SPL_SEPARATE_BSS
select SPL_SERIAL_SUPPORT
select SPL_DRIVERS_MISC_SUPPORT
- select ENABLE_ARM_SOC_BOOT0_HOOK
select DEBUG_UART_BOARD_INIT
help
The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72