diff options
| author | Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> | 2022-10-19 16:40:58 +0200 |
|---|---|---|
| committer | Quentin Schulz <quentin.schulz@theobroma-systems.com> | 2022-10-19 16:40:58 +0200 |
| commit | 57156aef3ee7bbc7785dd5ae148c80b5c16c5e69 (patch) | |
| tree | 0c1cd1a041b3e0bcc136b15e6a450a3a6a84e2d2 | |
| parent | afd158b8302be430728f73c21c2e4eb59dfb3a02 (diff) | |
TSD: arm64: dts: rockchip: lower rk3399-puma-haikou SD controller clock frequency
CRC errors (code -84 EILSEQ) have been observed for some SanDisk
Ultra A1 cards when running at 50MHz.
Waveform analysis suggest that the level shifters that are used on the
RK3399-Q7 module for voltage translation between 3.0 and 3.3V don't
handle clock rates at or above 48MHz properly. Back off to 40MHz for
some safety margin.
[TSD] Sent to Linux kernel first (see link), will be synced by upstream
U-Boot once merged.
Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Link: https://lore.kernel.org/lkml/20221019-upstream-puma-sd-40mhz-v1-0-754a76421518@theobroma-systems.com/
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
| -rw-r--r-- | arch/arm/dts/rk3399-puma-haikou.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/rk3399-puma-haikou.dts b/arch/arm/dts/rk3399-puma-haikou.dts index 292bb7e80c..1de351e378 100644 --- a/arch/arm/dts/rk3399-puma-haikou.dts +++ b/arch/arm/dts/rk3399-puma-haikou.dts @@ -207,7 +207,7 @@ cap-sd-highspeed; cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; disable-wp; - max-frequency = <150000000>; + max-frequency = <40000000>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; vmmc-supply = <&vcc3v3_baseboard>; |