px30-clk: separate clock init

1 files changed, 57 insertions, 50 deletions

diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
index 00bc6d8775..7117e49442 100644
--- a/drivers/clk/rockchip/clk_px30.c
+++ b/drivers/clk/rockchip/clk_px30.c
@@ -1098,8 +1098,12 @@ static int px30_clk_get_gpll_rate(ulong *rate)
 					  &pmucru_dev);
 	if (ret) {
 		printf("%s: could not find pmucru device\n", __func__);
+*rate = (1200 * 1000000);
+return 0;
+
 		return ret;
 	}
+
 	priv = dev_get_priv(pmucru_dev);
 	*rate =  priv->gpll_hz;
 
@@ -1370,17 +1374,20 @@ static int __maybe_unused px30_clk_set_parent(struct clk *clk, struct clk *paren
 static int px30_clk_enable(struct clk *clk)
 {
 	switch (clk->id) {
+	case HCLK_HOST:
 	case SCLK_GMAC:
 	case SCLK_GMAC_RX_TX:
 	case SCLK_MAC_REF:
 	case SCLK_MAC_REFOUT:
 	case ACLK_GMAC:
 	case PCLK_GMAC:
+	case SCLK_GMAC_RMII:
 		/* Required to successfully probe the Designware GMAC driver */
 		return 0;
 	}
 
 	debug("%s: unsupported clk %ld\n", __func__, clk->id);
+printf("%s: unsupported clk %ld\n", __func__, clk->id);
 	return -ENOENT;
 }
 
@@ -1393,6 +1400,26 @@ static struct clk_ops px30_clk_ops = {
 	.enable = px30_clk_enable,
 };
 
+static void px30_clk_init(struct px30_clk_priv *priv)
+{
+	struct udevice *cru_dev;
+	ulong npll_hz;
+	int ret;
+
+	npll_hz = px30_clk_get_pll_rate(priv, NPLL);
+	if (npll_hz != NPLL_HZ) {
+		ret = px30_clk_set_pll_rate(priv, NPLL, NPLL_HZ);
+		if (ret < 0)
+			printf("%s failed to set npll rate\n", __func__);
+	}
+
+	px30_bus_set_clk(priv, ACLK_BUS_PRE, ACLK_BUS_HZ);
+	px30_bus_set_clk(priv, HCLK_BUS_PRE, HCLK_BUS_HZ);
+	px30_bus_set_clk(priv, PCLK_BUS_PRE, PCLK_BUS_HZ);
+	px30_peri_set_clk(priv, ACLK_PERI_PRE, ACLK_PERI_HZ);
+	px30_peri_set_clk(priv, HCLK_PERI_PRE, HCLK_PERI_HZ);
+}
+
 static int px30_clk_probe(struct udevice *dev)
 {
 	struct px30_clk_priv *priv = dev_get_priv(dev);
@@ -1403,6 +1430,7 @@ static int px30_clk_probe(struct udevice *dev)
 		priv->armclk_enter_hz = px30_clk_get_pll_rate(priv, APLL);
 		priv->armclk_init_hz = priv->armclk_enter_hz;
 	}
+
 	if (px30_clk_get_pll_rate(priv, APLL) != APLL_HZ) {
 		ret = px30_armclk_set_clk(priv, APLL_HZ);
 		if (ret < 0)
@@ -1410,21 +1438,23 @@ static int px30_clk_probe(struct udevice *dev)
 		priv->armclk_init_hz = APLL_HZ;
 	}
 
-	/* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
-	ret = clk_set_defaults(dev);
-	if (ret)
-		debug("%s clk_set_defaults failed %d\n", __func__, ret);
-	else
-		priv->sync_kernel = true;
-
 	if (!priv->gpll_hz) {
 		ret = px30_clk_get_gpll_rate(&priv->gpll_hz);
 		if (ret) {
 			printf("%s failed to get gpll rate\n", __func__);
-			return ret;
+//			return ret;
 		}
 	}
 
+	px30_clk_init(priv);
+
+	/* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
+	ret = clk_set_defaults(dev);
+	if (ret)
+		debug("%s clk_set_defaults failed %d\n", __func__, ret);
+	else
+		priv->sync_kernel = true;
+
 	return 0;
 }
 
@@ -1533,29 +1563,29 @@ static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz)
 	ulong aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate;
 	int ret;
 
-	ret = uclass_get_device_by_name(UCLASS_CLK,
+/*	ret = uclass_get_device_by_name(UCLASS_CLK,
 					"clock-controller@ff2b0000",
 					 &cru_dev);
 	if (ret) {
 		printf("%s failed to get cru device\n", __func__);
 		return ret;
 	}
-	cru_priv = dev_get_priv(cru_dev);
+	cru_priv = dev_get_priv(cru_dev); */
 
 	if (priv->gpll_hz == hz)
 		return priv->gpll_hz;
 
-	cru_priv->gpll_hz = priv->gpll_hz;
+//	cru_priv->gpll_hz = priv->gpll_hz;
 	div = DIV_ROUND_UP(hz, priv->gpll_hz);
 
 	/* save clock rate */
-	aclk_bus_rate = px30_bus_get_clk(cru_priv, ACLK_BUS_PRE);
+/*	aclk_bus_rate = px30_bus_get_clk(cru_priv, ACLK_BUS_PRE);
 	hclk_bus_rate = px30_bus_get_clk(cru_priv, HCLK_BUS_PRE);
 	pclk_bus_rate = px30_bus_get_clk(cru_priv, PCLK_BUS_PRE);
 	aclk_peri_rate = px30_peri_get_clk(cru_priv, ACLK_PERI_PRE);
-	hclk_peri_rate = px30_peri_get_clk(cru_priv, HCLK_PERI_PRE);
+	hclk_peri_rate = px30_peri_get_clk(cru_priv, HCLK_PERI_PRE); */
 	pclk_pmu_rate = px30_pclk_pmu_get_pmuclk(priv);
-	debug("%s aclk_bus=%lu, hclk_bus=%lu, pclk_bus=%lu\n", __func__,
+/*	debug("%s aclk_bus=%lu, hclk_bus=%lu, pclk_bus=%lu\n", __func__,
 	      aclk_bus_rate, hclk_bus_rate, pclk_bus_rate);
 	debug("%s aclk_peri=%lu, hclk_peri=%lu, pclk_pmu=%lu\n", __func__,
 	      aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate);
@@ -1563,19 +1593,19 @@ static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz)
 	sdmmc_rate = px30_mmc_get_clk(cru_priv, SCLK_SDMMC);
 	nandc_rate = px30_nandc_get_clk(cru_priv);
 	debug("%s emmc=%lu, sdmmc=%lu, nandc=%lu\n", __func__,
-	      emmc_rate, sdmmc_rate, nandc_rate);
+	      emmc_rate, sdmmc_rate, nandc_rate); */
 
 	/* avoid rate too large, reduce rate first */
-	px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate / div);
+/*	px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate / div);
 	px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate / div);
 	px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate / div);
 	px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate / div);
-	px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate / div);
+	px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate / div); */
 	px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate / div);
 
-	px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate / div);
+/*	px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate / div);
 	px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate / div);
-	px30_nandc_set_clk(cru_priv, nandc_rate / div);
+	px30_nandc_set_clk(cru_priv, nandc_rate / div); */
 
 	/* change gpll rate */
 	rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz);
@@ -1583,16 +1613,16 @@ static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz)
 	cru_priv->gpll_hz = priv->gpll_hz;
 
 	/* restore clock rate */
-	px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate);
+/*	px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate);
 	px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate);
 	px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate);
 	px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate);
-	px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate);
+	px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate); */
 	px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate);
 
-	px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate);
+/*	px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate);
 	px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate);
-	px30_nandc_set_clk(cru_priv, nandc_rate);
+	px30_nandc_set_clk(cru_priv, nandc_rate); */
 
 	return priv->gpll_hz;
 }
@@ -1624,9 +1654,9 @@ static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate)
 
 	debug("%s %ld %ld\n", __func__, clk->id, rate);
 	switch (clk->id) {
-	case PLL_GPLL:
+/*	case PLL_GPLL:
 		ret = px30_gpll_set_pmuclk(priv, rate);
-		break;
+		break; */
 	case PCLK_PMU_PRE:
 		ret = px30_pclk_pmu_set_pmuclk(priv, rate);
 		break;
@@ -1642,10 +1672,9 @@ static struct clk_ops px30_pmuclk_ops = {
 	.set_rate = px30_pmuclk_set_rate,
 };
 
-static void px30_clk_init(struct px30_pmuclk_priv *priv)
+static void px30_pmuclk_init(struct px30_pmuclk_priv *priv)
 {
 	struct udevice *cru_dev;
-	struct px30_clk_priv *cru_priv;
 	ulong npll_hz;
 	int ret;
 
@@ -1656,28 +1685,6 @@ static void px30_clk_init(struct px30_pmuclk_priv *priv)
 			printf("%s failed to set gpll rate\n", __func__);
 	}
 
-	ret = uclass_get_device_by_name(UCLASS_CLK,
-					"clock-controller@ff2b0000",
-					 &cru_dev);
-	if (ret) {
-		printf("%s failed to get cru device\n", __func__);
-		return;
-	}
-	cru_priv = dev_get_priv(cru_dev);
-	cru_priv->gpll_hz = priv->gpll_hz;
-
-	npll_hz = px30_clk_get_pll_rate(cru_priv, NPLL);
-	if (npll_hz != NPLL_HZ) {
-		ret = px30_clk_set_pll_rate(cru_priv, NPLL, NPLL_HZ);
-		if (ret < 0)
-			printf("%s failed to set npll rate\n", __func__);
-	}
-
-	px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, ACLK_BUS_HZ);
-	px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, HCLK_BUS_HZ);
-	px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, PCLK_BUS_HZ);
-	px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, ACLK_PERI_HZ);
-	px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, HCLK_PERI_HZ);
 	px30_pclk_pmu_set_pmuclk(priv, PCLK_PMU_HZ);
 }
 
@@ -1686,7 +1693,7 @@ static int px30_pmuclk_probe(struct udevice *dev)
 	struct px30_pmuclk_priv *priv = dev_get_priv(dev);
 	int ret;
 
-	px30_clk_init(priv);
+	px30_pmuclk_init(priv);
 
 	/* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
 	ret = clk_set_defaults(dev);