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authorHeiko Stuebner <heiko@sntech.de>2019-07-17 11:58:08 +0200
committerHeiko Stuebner <heiko@sntech.de>2019-08-11 11:28:39 +0200
commita542748420ddbd6420515b5148da5bb860c2bfe2 (patch)
treea1982307d7d495773ce05164ab5cd7324d3c5554
parentebea2c47a1ddf8a8fd7bea4302c3d03825da47c4 (diff)
rockchip: ram: add dm-based sdram driver
sdram configuration happens outside of dm-infrastructure in special tpl-code, so the sdram driver itself has just the function to read back the sdram configuration and allow main uboot to handle dram sizes. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r--drivers/ram/rockchip/Makefile1
-rw-r--r--drivers/ram/rockchip/sdram_px30.c57
2 files changed, 58 insertions, 0 deletions
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index feb1f82d00..a51df57411 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_RAM_ROCKCHIP_DEBUG) += sdram_debug.o
obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
+obj-$(CONFIG_ROCKCHIP_PX30) = sdram_px30.o
obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c
new file mode 100644
index 0000000000..2d3ec5615f
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_px30.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_px30.h>
+#include <asm/arch-rockchip/sdram_common.h>
+
+struct dram_info {
+ struct ram_info info;
+ struct px30_pmugrf *pmugrf;
+};
+
+static int px30_dmc_probe(struct udevice *dev)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+ debug("%s: grf=%p\n", __func__, priv->pmugrf);
+ priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.size = rockchip_sdram_size(
+ (phys_addr_t)&priv->pmugrf->os_reg[2]);
+
+ return 0;
+}
+
+static int px30_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+
+ return 0;
+}
+
+static struct ram_ops px30_dmc_ops = {
+ .get_info = px30_dmc_get_info,
+};
+
+static const struct udevice_id px30_dmc_ids[] = {
+ { .compatible = "rockchip,px30-dmc" },
+ { }
+};
+
+U_BOOT_DRIVER(dmc_px30) = {
+ .name = "rockchip_px30_dmc",
+ .id = UCLASS_RAM,
+ .of_match = px30_dmc_ids,
+ .ops = &px30_dmc_ops,
+ .probe = px30_dmc_probe,
+ .priv_auto_alloc_size = sizeof(struct dram_info),
+};