fixup px30 clk

1 files changed, 31 insertions, 112 deletions

diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
index 7117e49442..d890b8811d 100644
--- a/drivers/clk/rockchip/clk_px30.c
+++ b/drivers/clk/rockchip/clk_px30.c
@@ -411,7 +411,7 @@ static void rational_best_approximation(
 static ulong px30_i2s_get_clk(struct px30_clk_priv *priv, ulong clk_id)
 {
 	u32 con, fracdiv, gate;
-	u32 clk_src = GPLL_HZ / 2;
+	u32 clk_src = priv->gpll_hz / 2;
 	unsigned long m, n;
 	struct px30_cru *cru = priv->cru;
 
@@ -441,7 +441,7 @@ static ulong px30_i2s_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz)
 	unsigned long m, n, val;
 	struct px30_cru *cru = priv->cru;
 
-	clk_src = GPLL_HZ / 2;
+	clk_src = priv->gpll_hz / 2;
 	rational_best_approximation(hz, clk_src,
 				    GENMASK(16 - 1, 0),
 				    GENMASK(16 - 1, 0),
@@ -1042,9 +1042,8 @@ static ulong px30_i2s1_mclk_set_clk(struct px30_clk_priv *priv, ulong clk_id,
 	return px30_i2s1_mclk_get_clk(priv, clk_id);
 }
 
-static ulong px30_mac_set_clk(struct clk *clk, uint hz)
+static ulong px30_mac_set_clk(struct px30_clk_priv *priv, uint hz)
 {
-	struct px30_clk_priv *priv = dev_get_priv(clk->dev);
 	struct px30_cru *cru = priv->cru;
 	u32 con = readl(&cru->clksel_con[22]);
 	ulong pll_rate;
@@ -1069,9 +1068,8 @@ static ulong px30_mac_set_clk(struct clk *clk, uint hz)
 	return DIV_TO_RATE(pll_rate, div);
 }
 
-static int px30_mac_set_speed_clk(struct clk *clk, uint hz)
+static int px30_mac_set_speed_clk(struct px30_clk_priv *priv, uint hz)
 {
-	struct px30_clk_priv *priv = dev_get_priv(clk->dev);
 	struct px30_cru *cru = priv->cru;
 
 	if (hz != 2500000 && hz != 25000000) {
@@ -1087,29 +1085,6 @@ static int px30_mac_set_speed_clk(struct clk *clk, uint hz)
 
 #endif
 
-static int px30_clk_get_gpll_rate(ulong *rate)
-{
-	struct udevice *pmucru_dev;
-	struct px30_pmuclk_priv *priv;
-	int ret;
-
-	ret = uclass_get_device_by_driver(UCLASS_CLK,
-					  DM_GET_DRIVER(rockchip_px30_pmucru),
-					  &pmucru_dev);
-	if (ret) {
-		printf("%s: could not find pmucru device\n", __func__);
-*rate = (1200 * 1000000);
-return 0;
-
-		return ret;
-	}
-
-	priv = dev_get_priv(pmucru_dev);
-	*rate =  priv->gpll_hz;
-
-	return 0;
-}
-
 static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv,
 				   enum px30_pll_id pll_id)
 {
@@ -1331,10 +1306,10 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong rate)
 		break;
 	case SCLK_GMAC:
 	case SCLK_GMAC_SRC:
-		ret = px30_mac_set_clk(clk, rate);
+		ret = px30_mac_set_clk(priv, rate);
 		break;
 	case SCLK_GMAC_RMII:
-		ret = px30_mac_set_speed_clk(clk, rate);
+		ret = px30_mac_set_speed_clk(priv, rate);
 		break;
 #endif
 	default:
@@ -1423,9 +1398,9 @@ static void px30_clk_init(struct px30_clk_priv *priv)
 static int px30_clk_probe(struct udevice *dev)
 {
 	struct px30_clk_priv *priv = dev_get_priv(dev);
+	struct clk clk_gpll;
 	int ret;
 
-	priv->sync_kernel = false;
 	if (!priv->armclk_enter_hz) {
 		priv->armclk_enter_hz = px30_clk_get_pll_rate(priv, APLL);
 		priv->armclk_init_hz = priv->armclk_enter_hz;
@@ -1438,22 +1413,18 @@ static int px30_clk_probe(struct udevice *dev)
 		priv->armclk_init_hz = APLL_HZ;
 	}
 
-	if (!priv->gpll_hz) {
-		ret = px30_clk_get_gpll_rate(&priv->gpll_hz);
-		if (ret) {
-			printf("%s failed to get gpll rate\n", __func__);
-//			return ret;
-		}
+	/* get the GPLL rate from the pmucru */
+	ret = clk_get_by_name(dev, "gpll", &clk_gpll);
+	if (ret) {
+		printf("%s: failed to get gpll clk from pmucru\n", __func__);
+		return ret;
 	}
 
-	px30_clk_init(priv);
+	priv->gpll_hz = clk_get_rate(&clk_gpll);
 
-	/* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
-	ret = clk_set_defaults(dev);
-	if (ret)
-		debug("%s clk_set_defaults failed %d\n", __func__, ret);
-	else
-		priv->sync_kernel = true;
+#ifdef CONFIG_SPL_BUILD
+	px30_clk_init(priv);
+#endif
 
 	return 0;
 }
@@ -1488,17 +1459,12 @@ static int px30_clk_bind(struct udevice *dev)
 		sys_child->priv = priv;
 	}
 
-	ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset",
-					 dev_ofnode(dev), &sf_child);
-	if (ret) {
-		debug("Warning: No rockchip reset driver: ret=%d\n", ret);
-	} else {
-		sf_priv = malloc(sizeof(struct softreset_reg));
-		sf_priv->sf_reset_offset = offsetof(struct px30_cru,
-						    softrst_con[0]);
-		sf_priv->sf_reset_num = 12;
-		sf_child->priv = sf_priv;
-	}
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
+	ret = offsetof(struct px30_cru, softrst_con[0]);
+	ret = rockchip_reset_bind(dev, ret, 12);
+	if (ret)
+		debug("Warning: software reset driver bind faile\n");
+#endif
 
 	return 0;
 }
@@ -1545,14 +1511,14 @@ static ulong px30_pclk_pmu_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz)
 	return px30_pclk_pmu_get_pmuclk(priv);
 }
 
-static ulong px30_gpll_get_pmuclk(struct px30_pmuclk_priv *priv)
+static ulong px30_pmuclk_get_gpll_rate(struct px30_pmuclk_priv *priv)
 {
 	struct px30_pmucru *pmucru = priv->pmucru;
 
 	return rkclk_pll_get_rate(&pmucru->pll, &pmucru->pmu_mode, GPLL);
 }
 
-static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz)
+static ulong px30_pmuclk_set_gpll_rate(struct px30_pmuclk_priv *priv, ulong hz)
 {
 	struct udevice *cru_dev;
 	struct px30_clk_priv *cru_priv;
@@ -1563,67 +1529,25 @@ static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz)
 	ulong aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate;
 	int ret;
 
-/*	ret = uclass_get_device_by_name(UCLASS_CLK,
-					"clock-controller@ff2b0000",
-					 &cru_dev);
-	if (ret) {
-		printf("%s failed to get cru device\n", __func__);
-		return ret;
-	}
-	cru_priv = dev_get_priv(cru_dev); */
-
 	if (priv->gpll_hz == hz)
 		return priv->gpll_hz;
 
-//	cru_priv->gpll_hz = priv->gpll_hz;
 	div = DIV_ROUND_UP(hz, priv->gpll_hz);
 
 	/* save clock rate */
-/*	aclk_bus_rate = px30_bus_get_clk(cru_priv, ACLK_BUS_PRE);
-	hclk_bus_rate = px30_bus_get_clk(cru_priv, HCLK_BUS_PRE);
-	pclk_bus_rate = px30_bus_get_clk(cru_priv, PCLK_BUS_PRE);
-	aclk_peri_rate = px30_peri_get_clk(cru_priv, ACLK_PERI_PRE);
-	hclk_peri_rate = px30_peri_get_clk(cru_priv, HCLK_PERI_PRE); */
 	pclk_pmu_rate = px30_pclk_pmu_get_pmuclk(priv);
-/*	debug("%s aclk_bus=%lu, hclk_bus=%lu, pclk_bus=%lu\n", __func__,
-	      aclk_bus_rate, hclk_bus_rate, pclk_bus_rate);
-	debug("%s aclk_peri=%lu, hclk_peri=%lu, pclk_pmu=%lu\n", __func__,
-	      aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate);
-	emmc_rate = px30_mmc_get_clk(cru_priv, SCLK_EMMC);
-	sdmmc_rate = px30_mmc_get_clk(cru_priv, SCLK_SDMMC);
-	nandc_rate = px30_nandc_get_clk(cru_priv);
-	debug("%s emmc=%lu, sdmmc=%lu, nandc=%lu\n", __func__,
-	      emmc_rate, sdmmc_rate, nandc_rate); */
 
 	/* avoid rate too large, reduce rate first */
-/*	px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate / div);
-	px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate / div);
-	px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate / div);
-	px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate / div);
-	px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate / div); */
 	px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate / div);
 
-/*	px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate / div);
-	px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate / div);
-	px30_nandc_set_clk(cru_priv, nandc_rate / div); */
-
 	/* change gpll rate */
 	rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz);
-	priv->gpll_hz = px30_gpll_get_pmuclk(priv);
+	priv->gpll_hz = px30_pmuclk_get_gpll_rate(priv);
 	cru_priv->gpll_hz = priv->gpll_hz;
 
 	/* restore clock rate */
-/*	px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate);
-	px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate);
-	px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate);
-	px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate);
-	px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate); */
 	px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate);
 
-/*	px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate);
-	px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate);
-	px30_nandc_set_clk(cru_priv, nandc_rate); */
-
 	return priv->gpll_hz;
 }
 
@@ -1635,7 +1559,7 @@ static ulong px30_pmuclk_get_rate(struct clk *clk)
 	debug("%s %ld\n", __func__, clk->id);
 	switch (clk->id) {
 	case PLL_GPLL:
-		rate = px30_gpll_get_pmuclk(priv);
+		rate = px30_pmuclk_get_gpll_rate(priv);
 		break;
 	case PCLK_PMU_PRE:
 		rate = px30_pclk_pmu_get_pmuclk(priv);
@@ -1654,9 +1578,9 @@ static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate)
 
 	debug("%s %ld %ld\n", __func__, clk->id, rate);
 	switch (clk->id) {
-/*	case PLL_GPLL:
-		ret = px30_gpll_set_pmuclk(priv, rate);
-		break; */
+	case PLL_GPLL:
+		ret = px30_pmuclk_set_gpll_rate(priv, rate);
+		break;
 	case PCLK_PMU_PRE:
 		ret = px30_pclk_pmu_set_pmuclk(priv, rate);
 		break;
@@ -1678,9 +1602,9 @@ static void px30_pmuclk_init(struct px30_pmuclk_priv *priv)
 	ulong npll_hz;
 	int ret;
 
-	priv->gpll_hz = px30_gpll_get_pmuclk(priv);
+	priv->gpll_hz = px30_pmuclk_get_gpll_rate(priv);
 	if (priv->gpll_hz != GPLL_HZ) {
-		ret = px30_gpll_set_pmuclk(priv, GPLL_HZ);
+		ret = px30_pmuclk_set_gpll_rate(priv, GPLL_HZ);
 		if (ret < 0)
 			printf("%s failed to set gpll rate\n", __func__);
 	}
@@ -1695,11 +1619,6 @@ static int px30_pmuclk_probe(struct udevice *dev)
 
 	px30_pmuclk_init(priv);
 
-	/* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
-	ret = clk_set_defaults(dev);
-	if (ret)
-		debug("%s clk_set_defaults failed %d\n", __func__, ret);
-
 	return 0;
 }