summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorHeiko Stuebner <heiko@sntech.de>2019-09-05 14:29:58 +0200
committerHeiko Stuebner <heiko@sntech.de>2019-09-05 14:29:58 +0200
commit0afd8182707e955c66358136c8cee416c2561de3 (patch)
treeacf1d827d4cf602f95b3d0533aa99ac973dea8fd
parentc3b13bb33f929c7b1301a9734c6e1eb0bf14d99e (diff)
sync px30.dtsi from kernel
-rw-r--r--arch/arm/dts/px30.dtsi79
1 files changed, 65 insertions, 14 deletions
diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
index 467a93383a..153549a190 100644
--- a/arch/arm/dts/px30.dtsi
+++ b/arch/arm/dts/px30.dtsi
@@ -200,13 +200,6 @@
clock-output-names = "xin24m";
};
- xin32k: xin32k {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "xin32k";
- };
-
pmu: power-management@ff000000 {
compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
reg = <0x0 0xff000000 0x0 0x1000>;
@@ -694,6 +687,19 @@
#reset-cells = <1>;
};
+ dsi_dphy: phy@ff2e0000 {
+ compatible = "rockchip,px30-dsi-dphy";
+ reg = <0x0 0xff2e0000 0x0 0x10000>;
+ clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
+ clock-names = "ref", "pclk";
+ #clock-cells = <0>;
+ resets = <&cru SRST_MIPIDSIPHY_P>;
+ reset-names = "apb";
+ #phy-cells = <0>;
+ power-domains = <&power PX30_PD_VO>;
+ status = "disabled";
+ };
+
usb20_otg: usb@ff300000 {
compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
"snps,dwc2";
@@ -792,10 +798,50 @@
clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
power-domains = <&power PX30_PD_MMC_NAND>;
status = "disabled";
};
+ dsi: dsi@ff450000 {
+ compatible = "rockchip,px30-mipi-dsi";
+ reg = <0x0 0xff450000 0x0 0x10000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_MIPI_DSI>, <&dsi_dphy>;
+ clock-names = "pclk", "pll";
+ resets = <&cru SRST_MIPIDSI_HOST_P>;
+ reset-names = "apb";
+ phys = <&dsi_dphy>;
+ phy-names = "dphy";
+ power-domains = <&power PX30_PD_VO>;
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_dsi>;
+ };
+
+ dsi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_dsi>;
+ };
+ };
+ };
+ };
+
vopb: vop@ff460000 {
compatible = "rockchip,px30-vop-big";
reg = <0x0 0xff460000 0x0 0xefc>;
@@ -813,6 +859,11 @@
vopb_out: port {
#address-cells = <1>;
#size-cells = <0>;
+
+ vopb_out_dsi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi_in_vopb>;
+ };
};
};
@@ -822,7 +873,7 @@
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
- clock-names = "aclk", "hclk";
+ clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
#iommu-cells = <0>;
status = "disabled";
@@ -845,6 +896,11 @@
vopl_out: port {
#address-cells = <1>;
#size-cells = <0>;
+
+ vopl_out_dsi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi_in_vopl>;
+ };
};
};
@@ -854,7 +910,7 @@
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
- clock-names = "aclk", "hclk";
+ clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
#iommu-cells = <0>;
status = "disabled";
@@ -1646,11 +1702,6 @@
<1 RK_PB2 2 &pcfg_pull_up_8ma>;
};
- emmc_pwren: emmc-pwren {
- rockchip,pins =
- <1 RK_PB0 2 &pcfg_pull_none>;
- };
-
emmc_rstnout: emmc-rstnout {
rockchip,pins =
<1 RK_PB3 2 &pcfg_pull_none>;