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authorAngela Stegmaier <angelabaker@ti.com>2015-02-16 10:15:55 +0530
committerTom Rini <trini@ti.com>2015-02-16 12:41:40 -0500
commitaa8ac43645243b69faf0e81fab5f0d6fcf4285cf (patch)
tree4375c1e8dc55b61a777dcbbdbb7e9939821e076f
parent89831112d46fb19127f3de9cec781e5a9c28b281 (diff)
ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock
DDR3 timing and latency paramenters were not configured correctly for 666MHz. Fixing the timing and latency values according to Data sheet. This fixes the random crashes seen on DRA72-evm. Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
-rw-r--r--arch/arm/cpu/armv7/omap5/sdram.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 7d8cec08c2..e5456ff7cb 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -186,18 +186,18 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
};
const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
- .sdram_config_init = 0x61851AB2,
- .sdram_config = 0x61851AB2,
+ .sdram_config_init = 0x61862B32,
+ .sdram_config = 0x61862B32,
.sdram_config2 = 0x08000000,
- .ref_ctrl = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x027F88A8,
+ .ref_ctrl = 0x0000144A,
+ .sdram_tim1 = 0xD113781C,
+ .sdram_tim2 = 0x308F7FE3,
+ .sdram_tim3 = 0x009F86A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400A,
- .emif_ddr_phy_ctlr_1 = 0x0024400A,
+ .emif_ddr_phy_ctlr_1_init = 0x0E24400D,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400D,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
.emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,