diff options
| author | Elaine Zhang <zhangqing@rock-chips.com> | 2019-04-09 17:35:43 +0800 |
|---|---|---|
| committer | Elaine Zhang <zhangqing@rock-chips.com> | 2019-04-09 17:39:21 +0800 |
| commit | 68d8964cb4ed53067599ec6739e8bfa5743e43c2 (patch) | |
| tree | fd83d2fca4852359e0ac675d31d3b877c4eb60d2 | |
| parent | 8afd7ff1e3da102bf2b387ae89a8c702129a85e2 (diff) | |
clk: rockchip: rk1808: support pclk_wdt get rate
Change-Id: Ib204b4c014c3b4cbd35d1f335378b0b399689303
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
| -rw-r--r-- | drivers/clk/rockchip/clk_rk1808.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk1808.c b/drivers/clk/rockchip/clk_rk1808.c index 9639065fc4..f9e51d0e04 100644 --- a/drivers/clk/rockchip/clk_rk1808.c +++ b/drivers/clk/rockchip/clk_rk1808.c @@ -583,6 +583,7 @@ static ulong rk1808_bus_get_clk(struct rk1808_clk_priv *priv, ulong clk_id) parent = priv->gpll_hz; break; case LSCLK_BUS_PRE: + case PCLK_WDT: con = readl(&cru->clksel_con[28]); div = (con & LSCLK_BUS_DIV_CON_MASK) >> LSCLK_BUS_DIV_CON_SHIFT; parent = priv->gpll_hz; @@ -822,6 +823,7 @@ static ulong rk1808_clk_get_rate(struct clk *clk) case HSCLK_BUS_PRE: case MSCLK_BUS_PRE: case LSCLK_BUS_PRE: + case PCLK_WDT: rate = rk1808_bus_get_clk(priv, clk->id); break; case MSCLK_PERI: |