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authorChristoph Muellner <christoph.muellner@theobroma-systems.com>2019-04-17 18:59:21 +0200
committerChristoph Muellner <christoph.muellner@theobroma-systems.com>2019-05-06 14:32:33 +0200
commitc2663a78ccda1dd87b5be8480fedcce4e04f4472 (patch)
tree67f3b8a5a18c2b8de66dd95afc840d822f9a3e9a
parent0298e0ffea2a9d7516ec35857fe56bf3ddaf9fd9 (diff)
rockchip: rk3399: Add option to print on UART3.
The RK3399 SPL does not use a pinctrl driver to setup the UART pins. Instead it works based on config macros, which set the base address of the actual UART block. Currently the RK3399 SPL support UART0 and UART2. This patch adds UART3 in the same way as UART0. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
-rw-r--r--arch/arm/mach-rockchip/rk3399-board-spl.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c
index 257cb0c8b6..4ebed6c18d 100644
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
@@ -146,6 +146,14 @@ void board_debug_uart_init(void)
rk_clrsetreg(&grf->gpio2c_iomux,
GRF_GPIO2C1_SEL_MASK,
GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
+ /* Enable early UART3 on the RK3399 */
+ rk_clrsetreg(&grf->gpio3b_iomux,
+ GRF_GPIO3B6_SEL_MASK,
+ GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio3b_iomux,
+ GRF_GPIO3B7_SEL_MASK,
+ GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
#else
# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
rk_setreg(&grf->io_vsel, 1 << 0);