rk3399: puma: Add support for DDR3-1600-4GB dual-rank.

This patch adds support for DDR3 with speed grade 1600,
capacity 4 GB on dual-rank devices.

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>

3 files changed, 151 insertions, 0 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 16595a95c8..3bb710732b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -90,6 +90,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3399-puma-ddr1333.dtb \
 	rk3399-puma-ddr1600.dtb \
 	rk3399-puma-ddr1600-4gb.dtb \
+	rk3399-puma-ddr1600-4gb-dr.dtb \
 	rk3399-puma-ddr1866.dtb \
 	rk3399-puma-ddr1866-4gb.dtb \
 	rk3399-rock960.dtb \
diff --git a/arch/arm/dts/rk3399-puma-ddr1600-4gb-dr.dts b/arch/arm/dts/rk3399-puma-ddr1600-4gb-dr.dts
new file mode 100644
index 0000000000..d8104a2673
--- /dev/null
+++ b/arch/arm/dts/rk3399-puma-ddr1600-4gb-dr.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+
+#include "rk3399-puma.dtsi"
+#include "rk3399-sdram-ddr3-1600-4gb-dr.dtsi"
+
diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1600-4gb-dr.dtsi b/arch/arm/dts/rk3399-sdram-ddr3-1600-4gb-dr.dtsi
new file mode 100644
index 0000000000..a6e669b9ee
--- /dev/null
+++ b/arch/arm/dts/rk3399-sdram-ddr3-1600-4gb-dr.dtsi
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) 2019 Theobroma Systems Design und Consulting GmbH
+ */
+
+&dmc {
+        /* This SPD models a DDR3-1866M speed-bin. */
+	theobroma-systems,spd-data = /bits/ 8 <
+		0x01 /* CRC covers 0~125, 128 bytes data */
+		0x10 /* revision level 1.0 */
+		0x0b /* DDR3 SDRAM */
+		0x0b /* module-specific section (bytes 60 ~ 116): LRDIMM */
+		0x35 /* 8 banks, 8 Gb devices */
+		0x21 /* 16 rows, 10 columns */
+		0x03 /* 1.35V and 1.5V operable */
+		0x0a /* 2 rank, x16 device-width */
+		0x02 /* 32 bit (primary) bus-width */
+		0x11 /* fine timebase: 1/1 = 1ps */
+		0x01 /* medium timebase dividend */
+		0x08 /* medium timebase divisor */
+		0x09 /* tCKmin(MTB) .. DDR-1866 */
+		0x00 /* */
+		0x54 /* CAS supported: CL=10, CL=8, CL=6 */
+		0x02 /* CAS supported: CL=13 */
+		0x70 /* tAAmin(MTB) */
+		0x78 /* tWRmin(MTB) */
+		0x70 /* tRCDmin(MTB) */
+		0x30 /* tRRDmin(MTB): 6.0 ns */
+		0x70 /* tRPmin(MTB) */
+		0x11 /* upper nibble for tRC (bits 7~4) and tRAS bits (3~0) */
+		0x10 /* tRASmin(MTB), LSB */
+		0x80 /* tRCmin(MTB), LSB */
+		0xF0 /* tRFCmin(MTB), LSB */
+		0x0A /* tRFCmin(MTB), MSB */
+		0x3C /* tWTRmin(MTB) */
+		0x3C /* tRTPmin(MTB) */
+		0x01 /* upper nibble for tFAWmin */
+		0x18 /* tFAWmin(MTB), LSB */
+		0x00 /* optional features: no DLL-Off, no RZQ/7, no RZQ/6 */
+		0x05 /* thermal/refresh: ASR, 85-95 @ 2x refresh, 0-95 degC */
+		0x00 /* no thermal sensor */
+		0x10 /* stacking/signal-loading: not specified */
+		0xca /* tCKmin(FTB) */
+		0xa6 /* tAAmin(FTB) */
+		0xa6 /* tRCDmin(FTB) */
+		0xa6 /* tRPmin(FTB) */
+		0xa6 /* tRCmin */
+		0x00 /* MAC: tMAW = 8192*tREFI, untested MAC */
+		0x00 /* reserved -- 39 */
+		0x00 /* reserved -- 40 */
+		0x00 /* reserved -- byte 42 */
+		0x00 /* reserved -- byte 43 */
+		0x00 /* reserved -- byte 44 */
+		0x00 /* reserved -- byte 45 */
+		0x00 /* reserved -- byte 46 */
+		0x00 /* reserved -- byte 47 */
+		0x00 /* reserved -- byte 48 */
+		0x00 /* reserved -- byte 49 */
+		0x00 /* reserved -- byte 50 */
+		0x00 /* reserved -- byte 51 */
+		0x00 /* reserved -- byte 52 */
+		0x00 /* reserved -- byte 53 */
+		0x00 /* reserved -- byte 54 */
+		0x00 /* reserved -- byte 55 */
+		0x00 /* reserved -- byte 56 */
+		0x00 /* reserved -- byte 57 */
+		0x00 /* reserved -- byte 58 */
+		0x00 /* reserved -- byte 59 */
+		0x00 /* 60 */
+		0x00 /* 61 */
+		0x1F /* not based on a JEDEC card reference design */
+		0x00 /* 63 */
+		0x00 /* 64 */
+		0x00 /* 65 */
+		0x00 /* 66 */
+		0x00 /* 67 */
+		0x00 /* 68 */
+		0x00 /* 69 */
+		0x00 /* 70 */
+		0x00 /* 71 */
+		0x16 /* 72: DDR3-800 and DDR3-1066: 34ohm drive-strength, 240ohm ODT */
+		0x33 /* 73: DDR3-800 and DDR3-1066: QxODT Control, enable for rank 1 */
+		0x00 /* 74 */
+		0x00 /* 75 */
+		0x00 /* 76 */
+		0x05 /* 77: MR1,2 for 800 & 1066: 60ohm Rtt_Nom, 34ohm drive */
+		0x00 /* 78 */
+		0x00 /* 79 */
+		0x00 /* 80 */
+		0x00 /* 81 */
+		0x00 /* 82 */
+		0x05 /* 83: MR1,2 for 1333 & 1600: 60ohm Rtt_Nom, 34ohm drive */
+		0x84 /* 84 */
+		0x85 /* 85 */
+		0x86 /* 86 */
+		0x87 /* 87 */
+		0x88 /* 88 */
+		0x05 /* 89: MR1,2 for 1866 & 2133: 60ohm Rtt_Nom, 34ohm drive */
+		0x90
+	>;
+
+	rockchip,sdram-params = <
+		0x1 /* ch0: rank */
+		0xa /* ch0: col */
+		0x3 /* ch0: bk */
+		0x2 /* ch0: bw */
+		0x1 /* ch0: dbw */
+		0x0 /* ch0: row_3_4 */
+		0x10 /* ch0: cs0_row */
+		0x10 /* ch0: cs1_row */
+		1 /* ch0: ddrconfig */
+		0x80151015 /* ch0: ddrtiminga0 */
+		0x14040902 /* ch0: ddrtimingb0 */
+		0x00000002 /* ch0: ddrtimingc0 */
+		0x00006346 /* ch0: devtodev0 */
+		0x0000004c /* ch0: ddrmode */
+		0x00000000 /* ch0: agingx0 */
+		0x1
+		0xa
+		0x3
+		0x2
+		0x1
+		0x0
+		0x10
+		0x10
+		1
+		0x80151015
+		0x14040902
+		0x00000002
+		0x00006346
+		0x0000004c
+		0x00000000
+		800 /* base: ddr_freq */
+		3 /* base: dramtype */
+		2 /* base: num_channels */
+		13 /* base: stride */
+		1 /* base: odt */
+	>;
+};
+