diff options
| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-04-28 14:24:36 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-05-09 12:41:47 +0200 |
| commit | 2981fa51a29eba762d346d4bd3abacf384fb1f9a (patch) | |
| tree | 95d3c1a44004c537a2025c02dff9af53af53c5a8 | |
| parent | 4f37c7e1bac04497d720c9bde952a915cfa45f1f (diff) | |
rockchip: clk: rk3399: allow requests for HDMI clocks
This allows requests (via the DTS) for PCLK_HDMI_CTRL/PCLK_VIO_GRF,
which are clock gates in the HDMI output path for the RK3399.
As these are enabled by default (i.e. after reset), we don't implement
any logic to actively open/close these clock gates and simply assume
that their reset-default has not been changed.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 4 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3399.c | 6 |
2 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index 8c5c7187ed..616bb88a8e 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -478,8 +478,8 @@ enum { GRF_DPHY_TX0_TXSTOPMODE_DIS = 0, GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12, - GRF_DPHY_TX0_TURNREQUEST_MASK = 0xf000 - << GRF_DPHY_TX0_TURNREQUEST_SHIFT, + GRF_DPHY_TX0_TURNREQUEST_MASK = + (0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT), GRF_DPHY_TX0_TURNREQUEST_EN = 0x1, GRF_DPHY_TX0_TURNREQUEST_DIS = 0, diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 42f94688ac..026ed4dde7 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -883,6 +883,8 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_UART2: return 24000000; break; + case PCLK_HDMI_CTRL: + break; case DCLK_VOP0: case DCLK_VOP1: break; @@ -923,6 +925,10 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SPI0...SCLK_SPI5: ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); break; + case PCLK_HDMI_CTRL: + case PCLK_VIO_GRF: + /* the PCLK gates for video are enabled by default */ + break; case DCLK_VOP0: case DCLK_VOP1: ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); |