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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
#include "rk3399.dtsi"
/ {
compatible = "rockchip,rk3399pro";
xin32k: xin32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "xin32k";
#clock-cells = <0>;
};
};
&dfi {
status = "okay";
};
&dmc {
status = "okay";
center-supply = <&vdd_log>;
upthreshold = <40>;
downdifferential = <20>;
system-status-freq = <
/*system status freq(KHz)*/
SYS_STATUS_NORMAL 800000
SYS_STATUS_REBOOT 528000
SYS_STATUS_SUSPEND 200000
SYS_STATUS_VIDEO_1080P 200000
SYS_STATUS_VIDEO_4K 600000
SYS_STATUS_VIDEO_4K_10B 800000
SYS_STATUS_PERFORMANCE 800000
SYS_STATUS_BOOST 400000
SYS_STATUS_DUALVIEW 600000
SYS_STATUS_ISP 600000
>;
vop-pn-msch-readlatency = <
/* plane_number readlatency */
0 0
4 0x20
>;
vop-bw-dmc-freq = <
/* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
0 762 200000
763 1893 400000
1894 3012 528000
3013 99999 800000
>;
auto-min-freq = <200000>;
};
&emmc_phy {
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pcie0 {
ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>;
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
supports-emmc;
non-removable;
keep-power-in-suspend;
mmc-hs400-enhanced-strobe;
status = "okay";
};
&sdio0 {
clock-frequency = <150000000>;
clock-freq-min-max = <200000 150000000>;
supports-sdio;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
status = "okay";
};
&sdmmc {
clock-frequency = <150000000>;
clock-freq-min-max = <400000 150000000>;
supports-sd;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
num-slots = <1>;
vqmmc-supply = <&vccio_sd>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
status = "okay";
};
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